Show patches with: Series = [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6       |   41 patches
Patch Series S/W/F Date Submitter Delegate State
[PULL,41/41] target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,40/41] target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,39/41] target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,38/41] hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,37/41] target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC) [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,36/41] target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8) [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,35/41] target/arm: Mark up VNCR offsets (offsets 0x100..0x160) [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,34/41] target/arm: Mark up VNCR offsets (offsets 0x0..0xff) [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,33/41] target/arm: Report VNCR_EL2 based faults correctly [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,32/41] target/arm: Implement FEAT_NV2 redirection of sysregs to RAM [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,31/41] target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,30/41] target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,29/41] target/arm: Implement VNCR_EL2 register [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,28/41] target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,27/41] target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,26/41] target/arm: Handle FEAT_NV page table attribute changes [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,25/41] target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,24/41] target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1} [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,23/41] target/arm: Always use arm_pan_enabled() when checking if PAN is enabled [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,22/41] target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1} [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,21/41] target/arm: Set SPSR_EL1.M correctly when nested virt is enabled [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,20/41] target/arm: Make NV reads of CurrentEL return EL2 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,19/41] target/arm: Trap sysreg accesses for FEAT_NV [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,18/41] target/arm: Move FPU/SVE/SME access checks up above ARM_CP_SPECIAL_MASK check [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,17/41] target/arm: Make EL2 cpreg accessfns safe for FEAT_NV EL1 accesses [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,16/41] target/arm: *_EL12 registers should UNDEF when HCR_EL2.E2H is 0 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,15/41] target/arm: Record correct opcode fields in cpreg for E2H aliases [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,14/41] target/arm: Allow use of upper 32 bits of TBFLAG_A64 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,13/41] target/arm: Always honour HCR_EL2.TSC when HCR_EL2.NV is set [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,12/41] target/arm: Enable trapping of ERET for FEAT_NV [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,11/41] target/arm: Implement HCR_EL2.AT handling [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,10/41] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,09/41] hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,08/41] target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,07/41] hw/arm: Add missing QOM parent for v7-M SoCs [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,06/41] hw/arm/socs: configure priority bits for existing SOCs [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,05/41] hw/arm/armv7m: alias the NVIC "num-prio-bits" property [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,04/41] hw/intc/armv7m_nvic: add "num-prio-bits" property [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,03/41] hw/arm: Add minimal support for the B-L475E-IOT01A board [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,02/41] hw/arm: Add minimal support for the STM32L4x5 SoC [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable