Show patches with: Series = None       |   9 patches
Patch Series S/W/F Date Submitter Delegate State
[PULL,27/29] target/riscv: Add checks for several RVC reserved operands Untitled series #20638 --- 2019-05-26 Palmer Dabbelt Accepted
[PULL,11/29] target/riscv: Remove spaces from register names Untitled series #20638 --- 2019-05-26 Palmer Dabbelt Accepted
[PULL,10/29] target/riscv: Split gen_arith_imm into functional and temp Untitled series #20638 --- 2019-05-26 Palmer Dabbelt Accepted
[PULL,09/29] target/riscv: Split RVC32 and RVC64 insns into separate files Untitled series #20638 --- 2019-05-26 Palmer Dabbelt Accepted
[PULL,08/29] target/riscv: Use pattern groups in insn16.decode Untitled series #20638 --- 2019-05-26 Palmer Dabbelt Accepted
[PULL,07/29] target/riscv: Merge argument decode for RVC shifti Untitled series #20638 --- 2019-05-26 Palmer Dabbelt Accepted
[PULL,06/29] target/riscv: Merge argument sets for insn32 and insn16 Untitled series #20638 --- 2019-05-26 Palmer Dabbelt Accepted
[PULL,05/29] target/riscv: Use --static-decode for decodetree Untitled series #20638 --- 2019-05-26 Palmer Dabbelt Accepted
[PULL,04/29] target/riscv: Name the argument sets for all of insn32 formats Untitled series #20638 --- 2019-05-26 Palmer Dabbelt Accepted