Show patches with: Submitter = Alistair Francis       |    State = Action Required       |   250 patches
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Patch Series S/W/F Date Submitter Delegate State
[PULL,v3,01/20] target/riscv: Generate nanboxed results from fp helpers [PULL,v3,01/20] target/riscv: Generate nanboxed results from fp helpers --- 2020-08-22 Alistair Francis New
[v1,1/1] core/register: Specify instance_size in the TypeInfo [v1,1/1] core/register: Specify instance_size in the TypeInfo --- 2020-08-22 Alistair Francis New
[PULL,v2,10/20] configure: Create symbolic links for pc-bios/*.elf files riscv-to-apply queue --- 2020-08-14 Alistair Francis New
[PULL,v2,06/20] target/riscv: Clean up fmv.w.x riscv-to-apply queue --- 2020-08-14 Alistair Francis New
[PULL,v2,05/20] target/riscv: Check nanboxed inputs in trans_rvf.inc.c riscv-to-apply queue --- 2020-08-14 Alistair Francis New
[PULL,v2,02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s riscv-to-apply queue --- 2020-08-14 Alistair Francis New
[PULL,20/20] hw/intc: ibex_plic: Honour source priorities riscv-to-apply queue --- 2020-08-12 Alistair Francis New
[PULL,19/20] hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines riscv-to-apply queue --- 2020-08-12 Alistair Francis New
[PULL,16/20] target/riscv: Fix the translation of physical address riscv-to-apply queue --- 2020-08-12 Alistair Francis New
[PULL,15/20] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv-to-apply queue --- 2020-08-12 Alistair Francis New
[PULL,11/20] roms/opensbi: Upgrade from v0.7 to v0.8 riscv-to-apply queue --- 2020-08-12 Alistair Francis New
[PULL,09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64 riscv-to-apply queue --- 2020-08-12 Alistair Francis New
[PULL,08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device riscv-to-apply queue --- 2020-08-12 Alistair Francis New
[PULL,07/20] target/riscv: check before allocating TCG temps riscv-to-apply queue --- 2020-08-12 Alistair Francis New
[v3,11/13] target/riscv: Support the v0.6 Hypervisor extension CRSs RISC-V: Update the Hypervisor spec to v0.6.1 --- 2020-08-12 Alistair Francis New
[v3,07/13] target/riscv: Update the Hypervisor trap return/entry RISC-V: Update the Hypervisor spec to v0.6.1 --- 2020-08-12 Alistair Francis New
[v3,03/13] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions RISC-V: Update the Hypervisor spec to v0.6.1 --- 2020-08-12 Alistair Francis New
[v3,02/13] target/riscv: Allow generating hlv/hlvx/hsv instructions RISC-V: Update the Hypervisor spec to v0.6.1 --- 2020-08-12 Alistair Francis New
[v1,1/3] hw/intc: ibex_plic: Update the pending irqs hw/intc: A few fixes for the Ibex PLIC --- 2020-07-25 Alistair Francis New
[PULL,3/5] target/riscv: fix vector index load/store constraints [PULL,1/5] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH --- 2020-07-22 Alistair Francis New
[PULL,2/5] target/riscv: Quiet Coverity complains about vamo* [PULL,1/5] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH --- 2020-07-22 Alistair Francis New
[PULL,1/5] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH [PULL,1/5] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH --- 2020-07-22 Alistair Francis New
[PULL,15/15] target/riscv: Fix pmp NA4 implementation Untitled series #58977 --- 2020-07-14 Alistair Francis New
[PULL,10/15] target/riscv: fix return value of do_opivx_widen() Untitled series #58977 --- 2020-07-14 Alistair Francis New
[PULL,07/15] hw/riscv: Modify MROM size to end at 0x10000 Untitled series #58977 --- 2020-07-14 Alistair Francis New
[PULL,05/15] riscv: Add opensbi firmware dynamic support Untitled series #58977 --- 2020-07-14 Alistair Francis New
[PULL,04/15] RISC-V: Copy the fdt in dram instead of ROM Untitled series #58977 --- 2020-07-14 Alistair Francis New
[PULL,02/15] hw/riscv: virt: Sort the SoC memmap table entries Untitled series #58977 --- 2020-07-14 Alistair Francis New
[v2,v2,2/2] hw/char: Convert the Ibex UART to use the registerfields API [v2,v2,1/2] hw/char: Convert the Ibex UART to use the qdev Clock model --- 2020-07-09 Alistair Francis New
[v2,v2,1/2] hw/char: Convert the Ibex UART to use the qdev Clock model [v2,v2,1/2] hw/char: Convert the Ibex UART to use the qdev Clock model --- 2020-07-09 Alistair Francis New
[PULL,v2,57/64] target/riscv: vector element index instruction [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,56/64] target/riscv: vector iota instruction [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,49/64] target/riscv: vector wideing integer reduction instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,48/64] target/riscv: vector single-width integer reduction instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,46/64] target/riscv: widening floating-point/integer type-convert instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,44/64] target/riscv: vector floating-point merge instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,42/64] target/riscv: vector floating-point compare instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,40/64] target/riscv: vector floating-point min/max instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,38/64] target/riscv: vector widening floating-point fused multiply-add instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,37/64] target/riscv: vector single-width floating-point fused multiply-add instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,23/64] target/riscv: vector widening integer multiply instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,21/64] target/riscv: vector single-width integer multiply instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,18/64] target/riscv: vector narrowing integer right shift instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,12/64] target/riscv: add vector amo operations [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,10/64] target/riscv: add vector index load and store instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,09/64] target/riscv: add vector stride load and store instructions [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[PULL,v2,08/64] target/riscv: add an internals.h header [PULL,v2,01/64] riscv: plic: Honour source priorities --- 2020-07-02 Alistair Francis New
[v1,3/3] target/riscv: Regen floating point rounding mode in dynamic mode [v1,1/3] hw/char: Convert the Ibex UART to use the qdev Clock model --- 2020-06-30 Alistair Francis New
[v1,1/3] hw/char: Convert the Ibex UART to use the qdev Clock model [v1,1/3] hw/char: Convert the Ibex UART to use the qdev Clock model --- 2020-06-30 Alistair Francis New
[PULL,62/63] target/riscv: vector compress instruction riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,61/63] target/riscv: vector register gather instruction riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,60/63] target/riscv: vector slide instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,59/63] target/riscv: floating-point scalar move instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,58/63] target/riscv: integer scalar move instruction riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,57/63] target/riscv: integer extract instruction riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,54/63] target/riscv: set-X-first mask bit riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,51/63] target/riscv: vector mask-register logical instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,46/63] target/riscv: narrowing floating-point/integer type-convert instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,44/63] target/riscv: vector floating-point/integer type-convert instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,40/63] target/riscv: vector floating-point sign-injection instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,38/63] target/riscv: vector floating-point square-root instruction riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,35/63] target/riscv: vector widening floating-point multiply riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,34/63] target/riscv: vector single-width floating-point multiply/divide instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,33/63] target/riscv: vector widening floating-point add/subtract instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,31/63] target/riscv: vector narrowing fixed-point clip instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,30/63] target/riscv: vector single-width scaling shift instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,28/63] target/riscv: vector single-width fractional multiply with rounding and saturation riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,27/63] target/riscv: vector single-width averaging add and subtract riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,26/63] target/riscv: vector single-width saturating add and subtract riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,24/63] target/riscv: vector widening integer multiply-add instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,23/63] target/riscv: vector single-width integer multiply-add instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,21/63] target/riscv: vector integer divide instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,19/63] target/riscv: vector integer min/max instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,18/63] target/riscv: vector integer comparison instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,15/63] target/riscv: vector bitwise logical instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,14/63] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,12/63] target/riscv: vector single-width integer add and subtract riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,06/63] target/riscv: add vector configure instruction riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,04/63] target/riscv: implementation-defined constant parameters riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,02/63] riscv: plic: Add a couple of mising sifive_plic_update calls riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,01/63] riscv: plic: Honour source priorities riscv-to-apply queue --- 2020-06-26 Alistair Francis New
[PULL,v2,30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state Untitled series #59628 --- 2020-06-19 Alistair Francis New
[PULL,v2,27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Untitled series #59628 --- 2020-06-19 Alistair Francis New
[PULL,v2,23/32] hw/riscv: sifive_u: Hook a GPIO controller Untitled series #59628 --- 2020-06-19 Alistair Francis New
[PULL,v2,20/32] hw/riscv: sifive_u: Generate device tree node for OTP Untitled series #59628 --- 2020-06-19 Alistair Francis New
[PULL,v2,19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Untitled series #59628 --- 2020-06-19 Alistair Francis New
[PULL,v2,15/32] riscv/opentitan: Connect the UART device Untitled series #59628 --- 2020-06-19 Alistair Francis New
[PULL,v2,14/32] riscv/opentitan: Connect the PLIC device Untitled series #59628 --- 2020-06-19 Alistair Francis New
[PULL,31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,28/32] target/riscv: Rename IBEX CPU init routine [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,21/32] hw/riscv: sifive_gpio: Clean up the codes [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,11/32] riscv/opentitan: Fix the ROM size [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,09/32] target/riscv: Move the hfence instructions to the rvh decode [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,07/32] target/riscv: Set access as data_load when validating stage-2 PTEs [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
[PULL,06/32] riscv: Keep the CPU init routine names consistent [PULL,01/32] riscv: Add helper to make NaN-boxing for FP register --- 2020-06-19 Alistair Francis New
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