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envelope-from=prvs=558518344=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/23 11:44:34 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The RISC-V QEMU port currently has lot of preprocessor directives that check if we are targetting a 32-bit or 64-bit CPU. This means that the 64-bit RISC-V target can not run 32-bit CPUs. This is different to most other QEMU architectures and doesn't allow us to mix xlens (such as when running Hypervisors with different xlen guests). This series is a step toward removing some of those to allow us to use 32-bit CPUs on 64-bit RISC-V targets. Alistair Francis (16): target/riscv: Add a TYPE_RISCV_CPU_BASE CPU riscv: spike: Remove target macro conditionals riscv: virt: Remove target macro conditionals hw/riscv: boot: Remove compile time XLEN checks hw/riscv: virt: Remove compile time XLEN checks hw/riscv: spike: Remove compile time XLEN checks hw/riscv: sifive_u: Remove compile time XLEN checks target/riscv: fpu_helper: Match function defs in HELPER macros target/riscv: Add a riscv_cpu_is_32bit() helper function target/riscv: Specify the XLEN for CPUs target/riscv: cpu: Remove compile time XLEN checks target/riscv: cpu_helper: Remove compile time XLEN checks target/riscv: csr: Remove compile time XLEN checks target/riscv: cpu: Set XLEN independently from target target/riscv: Convert the get/set_field() to support 64-bit values target/riscv: Consolidate *statush registers include/hw/riscv/boot.h | 8 +- include/hw/riscv/spike.h | 6 -- include/hw/riscv/virt.h | 6 -- target/riscv/cpu.h | 36 ++++--- target/riscv/cpu_bits.h | 24 ++--- hw/riscv/boot.c | 55 ++++++----- hw/riscv/sifive_u.c | 59 ++++++------ hw/riscv/spike.c | 50 +++++----- hw/riscv/virt.c | 36 +++---- target/riscv/cpu.c | 83 ++++++++++------ target/riscv/cpu_helper.c | 47 +++------ target/riscv/csr.c | 197 ++++++++++++++++++++------------------ target/riscv/fpu_helper.c | 16 ++-- target/riscv/op_helper.c | 11 +-- 14 files changed, 328 insertions(+), 306 deletions(-) Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Bin Meng Reviewed-by: Bin Meng Tested-by: Bin Meng