mbox series

[v1,0/5] Fix the Hypervisor access functions

Message ID cover.1603466725.git.alistair.francis@wdc.com
Headers show
Series Fix the Hypervisor access functions | expand

Message

Alistair Francis Oct. 23, 2020, 3:25 p.m. UTC 
Richard pointed out that the Hypervisor access functions don't work
correctly, see:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg751540.html.
This seris fixes them up by adding a new MMU index for the virtualised
state.

Alistair Francis (5):
  target/riscv: Add a virtualised MMU Mode
  target/riscv: Set the virtualised MMU mode when doing hyp accesses
  target/riscv: Remove the HS_TWO_STAGE flag
  target/riscv: Remove the hyp load and store functions
  target/riscv: Split the Hypervisor execute load helpers

 target/riscv/cpu-param.h                |   2 +-
 target/riscv/cpu.h                      |   7 +-
 target/riscv/cpu_bits.h                 |   1 -
 target/riscv/helper.h                   |   6 +-
 target/riscv/cpu_helper.c               |  67 ++++++-------
 target/riscv/op_helper.c                |  90 ++---------------
 target/riscv/insn_trans/trans_rvh.c.inc | 127 +++++++-----------------
 7 files changed, 82 insertions(+), 218 deletions(-)

Comments

Alistair Francis Oct. 23, 2020, 11:29 p.m. UTC | #1 
On Fri, Oct 23, 2020 at 12:13 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 10/23/20 8:26 AM, Alistair Francis wrote:
> > +++ b/target/riscv/cpu-param.h
> > @@ -18,6 +18,6 @@
> >  # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
> >  #endif
> >  #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
> > -#define NB_MMU_MODES 4
> > +#define NB_MMU_MODES 8
>
> Is there really a PRV_M + virt enabled state?

No, there isn't.

>
> > +#define TB_FLAGS_PRIV_MMU_MASK                3
> ...
> > -    int mode = mmu_idx;
> > +    int mode = mmu_idx & 0x3;
>
> Use that MASK here?

Good idea.

Alistair

>
>
> r~