mbox series

[v2,0/4] Allow loading a no MMU kernel

Message ID cover.1602634524.git.alistair.francis@wdc.com
Headers show
Series Allow loading a no MMU kernel | expand

Message

Alistair Francis Oct. 14, 2020, 12:17 a.m. UTC 
This series allows loading a noMMU kernel using the -kernel option.
Currently if using -kernel QEMU assumes you also have firmware and loads
the kernel at a hardcoded offset. This series changes that so we only
load the kernel at an offset if a firmware (-bios) was loaded.

This series also adds a function to check if the CPU is 32-bit. This is
a step towards running 32-bit and 64-bit CPUs on the 64-bit RISC-V build
by using run time checks instead of compile time checks. We also allow
the user to sepcify a CPU for the sifive_u machine.

Alistair Francis (4):
  hw/riscv: sifive_u: Allow specifying the CPU
  hw/riscv: Return the end address of the loaded firmware
  hw/riscv: Add a riscv_is_32_bit() function
  hw/riscv: Load the kernel after the firmware

 include/hw/riscv/boot.h     | 13 ++++++---
 include/hw/riscv/sifive_u.h |  1 +
 hw/riscv/boot.c             | 56 ++++++++++++++++++++++++++-----------
 hw/riscv/opentitan.c        |  3 +-
 hw/riscv/sifive_e.c         |  3 +-
 hw/riscv/sifive_u.c         | 28 ++++++++++++++-----
 hw/riscv/spike.c            | 11 ++++++--
 hw/riscv/virt.c             | 11 ++++++--
 8 files changed, 91 insertions(+), 35 deletions(-)

Comments

Bin Meng Oct. 20, 2020, 3:17 a.m. UTC | #1 
On Wed, Oct 14, 2020 at 8:28 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Instead of loading the kernel at a hardcoded start address, let's load
> the kernel at the next alligned address after the end of the firmware.

typo of "aligned"

>
> This should have no impact for current users of OpenSBI, but will
> allow loading a noMMU kernel at the start of memory.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  include/hw/riscv/boot.h |  3 +++
>  hw/riscv/boot.c         | 19 ++++++++++++++-----
>  hw/riscv/opentitan.c    |  3 ++-
>  hw/riscv/sifive_e.c     |  3 ++-
>  hw/riscv/sifive_u.c     | 10 ++++++++--
>  hw/riscv/spike.c        | 11 ++++++++---
>  hw/riscv/virt.c         | 11 ++++++++---
>  7 files changed, 45 insertions(+), 15 deletions(-)
>

Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Alistair Francis Oct. 20, 2020, 3:44 p.m. UTC | #2 
On Tue, Oct 13, 2020 at 5:28 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> This series allows loading a noMMU kernel using the -kernel option.
> Currently if using -kernel QEMU assumes you also have firmware and loads
> the kernel at a hardcoded offset. This series changes that so we only
> load the kernel at an offset if a firmware (-bios) was loaded.
>
> This series also adds a function to check if the CPU is 32-bit. This is
> a step towards running 32-bit and 64-bit CPUs on the 64-bit RISC-V build
> by using run time checks instead of compile time checks. We also allow
> the user to sepcify a CPU for the sifive_u machine.
>
> Alistair Francis (4):
>   hw/riscv: sifive_u: Allow specifying the CPU
>   hw/riscv: Return the end address of the loaded firmware
>   hw/riscv: Add a riscv_is_32_bit() function
>   hw/riscv: Load the kernel after the firmware

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  include/hw/riscv/boot.h     | 13 ++++++---
>  include/hw/riscv/sifive_u.h |  1 +
>  hw/riscv/boot.c             | 56 ++++++++++++++++++++++++++-----------
>  hw/riscv/opentitan.c        |  3 +-
>  hw/riscv/sifive_e.c         |  3 +-
>  hw/riscv/sifive_u.c         | 28 ++++++++++++++-----
>  hw/riscv/spike.c            | 11 ++++++--
>  hw/riscv/virt.c             | 11 ++++++--
>  8 files changed, 91 insertions(+), 35 deletions(-)
>
> --
> 2.28.0
>