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13 Aug 2020 03:23:14 +0800 IronPort-SDR: Kk1j1/poCnJquLAYbxEmPdMHKHitkv/2A3IMdMRry50RoOHQKczZ1ofaReEAGAzBDIk1IFxlWq /IeMROIJzbbA== Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2020 12:11:05 -0700 IronPort-SDR: ouxOJtNHygGGPjl2PE4G4jTdAg2v3nKGkTIwjDZE8E1F2H8trmeetbpXlwbpWFVW/PnlcuGY+H HJEUmcBBbhqg== WDCIronportException: Internal Received: from jbfyk72.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.14]) by uls-op-cesaip01.wdc.com with ESMTP; 12 Aug 2020 12:23:14 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1 Date: Wed, 12 Aug 2020 12:13:14 -0700 Message-Id: X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=486123ee4=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/12 15:23:14 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, anup.patel@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This series updates the experimental QEMU RISC-V Hypervisor spec to the v0.6.1 draft implementation. THis includes support for the new 2-stage lookup instructions and the new CSRs. It also includes the new 0.6.1 support for the virtual instruction fault. This was tested by running 32-bit and 64-bit Xvisor on QEMU and starting Linux guests. v3: - Rebase on master v2: - Update to v0.6.1 Alistair Francis (13): target/riscv: Allow setting a two-stage lookup in the virt status target/riscv: Allow generating hlv/hlvx/hsv instructions target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions target/riscv: Don't allow guest to write to htinst target/riscv: Convert MSTATUS MTL to GVA target/riscv: Fix the interrupt cause code target/riscv: Update the Hypervisor trap return/entry target/riscv: Update the CSRs to the v0.6 Hyp extension target/riscv: Only support a single VSXL length target/riscv: Only support little endian guests target/riscv: Support the v0.6 Hypervisor extension CRSs target/riscv: Return the exception from invalid CSR accesses target/riscv: Support the Virtual Instruction fault target/riscv/cpu.h | 2 + target/riscv/cpu_bits.h | 25 +- target/riscv/helper.h | 4 + target/riscv/insn32-64.decode | 5 + target/riscv/insn32.decode | 11 + target/riscv/cpu_helper.c | 123 +++++---- target/riscv/csr.c | 171 ++++++++++-- target/riscv/insn_trans/trans_rvh.inc.c | 342 +++++++++++++++++++++++- target/riscv/op_helper.c | 176 +++++++++++- target/riscv/translate.c | 10 - 10 files changed, 761 insertions(+), 108 deletions(-)