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d="scan'208";a="139561706" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 05 Jun 2020 09:29:31 +0800 IronPort-SDR: HWI1x0nrR963ruZWia//Sslqsc8jOI8xIZiKl+8LPERnQu5sRwahWPVN+xUERnTq7WhKvLv9iP pg2EpvT/aRzOMChCOQ9d1IhW7aKe1NnjA= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2020 18:19:06 -0700 IronPort-SDR: tWb75yk9iw0OSWwvGHklT3AsPGuwXhPkry1SXi3u/0AlIaFg3Y2p/CUOipQ/9roOQT2wM59nNK vHWKn4rn7ssQ== WDCIronportException: Internal Received: from cnf006056.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.57.233]) by uls-op-cesaip01.wdc.com with ESMTP; 04 Jun 2020 18:29:30 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 00/17] RISC-V: Update the Hypervisor spec to v0.6.1 Date: Thu, 4 Jun 2020 18:20:42 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=4185f83b6=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/04 21:29:30 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, anup.pate@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis This series updates the experimental QEMU RISC-V Hypervisor spec to the v0.6.1 draft implementation. THis includes support for the new 2-stage lookup instructions and the new CSRs. It also includes the new 0.6.1 support for the virtual instruction fault. This was tested by running 32-bit and 64-bit Xvisor on QEMU and starting Linux guests. v2: - Update to v0.6.1 Alistair Francis (17): target/riscv: Set access as data_load when validating stage-2 PTEs target/riscv: Report errors validating 2nd-stage PTEs target/riscv: Move the hfence instructions to the rvh decode target/riscv: Implement checks for hfence target/riscv: Allow setting a two-stage lookup in the virt status target/riscv: Allow generating hlv/hlvx/hsv instructions target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions target/riscv: Don't allow guest to write to htinst target/riscv: Convert MSTATUS MTL to GVA target/riscv: Fix the interrupt cause code target/riscv: Update the Hypervisor trap return/entry target/riscv: Update the CSRs to the v0.6 Hyp extension target/riscv: Only support a single VSXL length target/riscv: Only support little endian guests target/riscv: Support the v0.6 Hypervisor extension CRSs target/riscv: Return the exception from invalid CSR accesses target/riscv: Support the Virtual Instruction fault target/riscv/cpu.h | 2 + target/riscv/cpu_bits.h | 25 +- target/riscv/helper.h | 9 + target/riscv/insn32-64.decode | 5 + target/riscv/insn32.decode | 19 +- target/riscv/cpu_helper.c | 114 +++--- target/riscv/csr.c | 171 ++++++-- .../riscv/insn_trans/trans_privileged.inc.c | 38 -- target/riscv/insn_trans/trans_rvh.inc.c | 377 ++++++++++++++++++ target/riscv/op_helper.c | 189 ++++++++- target/riscv/translate.c | 11 +- 11 files changed, 815 insertions(+), 145 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvh.inc.c