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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa493207sm15562711f8f.79.2025.04.22.07.55.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Apr 2025 07:55:03 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Pierrick Bouvier Cc: Richard Henderson , Anton Johansson Subject: [RFC PATCH v4 00/19] single-binary: Make hw/arm/ common Date: Tue, 22 Apr 2025 16:54:42 +0200 Message-ID: <20250422145502.70770-1-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since v3 - QAPI structure renamed as QemuTargetInfo - MachineClass::get_valid_cpu_types() runtime - target_aarch64() checking SysEmuTarget value - Remove CONFIG_TCG #ifdef'ry in hw/arm/ Since v2: - More comments from Pierrick addressed - Use GList to register valid CPUs list - Remove all TARGET_AARCH64 uses in hw/arm/ Since v1: - Dropped unrelated / irrelevant patches - Addressed Pierrick comments - Added R-b tag - Only considering machines, not CPUs. Hi, At this point this series is mostly a draft for Pierrick. After introducing the generic TargetInfo API [*], we implement the ARM variants, then use the API to remove target-specific code, allowing to eventually remove the target-specific arm_ss[] source set in meson.build, having all objects in arm_common_ss[]. Regards, Phil. Available here, based on tcg-next: https://gitlab.com/philmd/qemu/-/tags/single-binary-hw-arm-rfc-v4 Philippe Mathieu-Daudé (19): qapi: Rename TargetInfo structure as QemuTargetInfo qemu: Convert target_name() to TargetInfo API system/vl: Filter machine list available for a particular target binary hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries meson: Prepare to accept per-binary TargetInfo structure implementation config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) hw/arm/aspeed: Build objects once hw/arm/raspi: Build objects once hw/core/machine: Allow dynamic registration of valid CPU types hw/arm/virt: Register valid CPU types dynamically hw/arm/virt: Check accelerator availability at runtime qemu/target_info: Add %target_arch field to TargetInfo qemu/target_info: Add target_aarch64() helper hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() hw/core: Get default_cpu_type calling machine_class_default_cpu_type() hw/core: Introduce MachineClass::get_default_cpu_type() helper hw/arm/virt: Get default CPU type at runtime MAINTAINERS | 8 +++ meson.build | 11 +++ qapi/machine.json | 10 +-- include/hw/arm/machines-qom.h | 18 +++++ include/hw/boards.h | 10 +++ include/hw/core/cpu.h | 2 - include/qemu/target-info-impl.h | 35 +++++++++ include/qemu/target-info.h | 34 +++++++++ configs/targets/aarch64-softmmu.c | 23 ++++++ configs/targets/arm-softmmu.c | 23 ++++++ cpu-target.c | 5 -- hw/arm/aspeed.c | 115 ++++++++++++++++++++++++++++-- hw/arm/b-l475e-iot01a.c | 6 ++ hw/arm/bananapi_m2u.c | 6 ++ hw/arm/bcm2836.c | 5 +- hw/arm/collie.c | 6 ++ hw/arm/cubieboard.c | 6 ++ hw/arm/digic_boards.c | 6 ++ hw/arm/exynos4_boards.c | 11 +++ hw/arm/fby35.c | 6 ++ hw/arm/highbank.c | 11 +++ hw/arm/imx25_pdk.c | 6 ++ hw/arm/imx8mp-evk.c | 5 ++ hw/arm/integratorcp.c | 6 ++ hw/arm/kzm.c | 6 ++ hw/arm/mcimx6ul-evk.c | 6 ++ hw/arm/mcimx7d-sabre.c | 6 ++ hw/arm/microbit.c | 6 ++ hw/arm/mps2-tz.c | 21 ++++++ hw/arm/mps2.c | 21 ++++++ hw/arm/mps3r.c | 6 ++ hw/arm/msf2-som.c | 6 ++ hw/arm/musca.c | 11 +++ hw/arm/musicpal.c | 6 ++ hw/arm/netduino2.c | 6 ++ hw/arm/netduinoplus2.c | 6 ++ hw/arm/npcm7xx_boards.c | 26 +++++++ hw/arm/npcm8xx_boards.c | 5 ++ hw/arm/olimex-stm32-h405.c | 6 ++ hw/arm/omap_sx1.c | 11 +++ hw/arm/orangepi.c | 6 ++ hw/arm/raspi.c | 28 ++++++-- hw/arm/raspi4b.c | 5 ++ hw/arm/realview.c | 21 ++++++ hw/arm/sabrelite.c | 6 ++ hw/arm/sbsa-ref.c | 5 ++ hw/arm/stellaris.c | 11 +++ hw/arm/stm32vldiscovery.c | 6 ++ hw/arm/versatilepb.c | 11 +++ hw/arm/vexpress.c | 11 +++ hw/arm/virt.c | 78 +++++++++++--------- hw/arm/xilinx_zynq.c | 6 ++ hw/arm/xlnx-versal-virt.c | 5 ++ hw/arm/xlnx-zcu102.c | 5 ++ hw/core/machine-qmp-cmds.c | 10 +-- hw/core/machine.c | 37 ++++++++++ hw/core/null-machine.c | 6 ++ plugins/loader.c | 2 +- system/vl.c | 7 +- target-info-qom.c | 24 +++++++ target-info-stub.c | 22 ++++++ target-info.c | 26 +++++++ target/ppc/cpu_init.c | 2 +- configs/targets/meson.build | 3 + hw/arm/meson.build | 12 ++-- 65 files changed, 813 insertions(+), 71 deletions(-) create mode 100644 include/hw/arm/machines-qom.h create mode 100644 include/qemu/target-info-impl.h create mode 100644 include/qemu/target-info.h create mode 100644 configs/targets/aarch64-softmmu.c create mode 100644 configs/targets/arm-softmmu.c create mode 100644 target-info-qom.c create mode 100644 target-info-stub.c create mode 100644 target-info.c create mode 100644 configs/targets/meson.build