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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7390611d3d6sm11111321b3a.94.2025.03.25.15.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Mar 2025 15:44:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH v2 00/11] target/avr: Increase page size Date: Tue, 25 Mar 2025 15:43:52 -0700 Message-ID: <20250325224403.4011975-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For single-binary, we would really like to have a common TARGET_PAGE_BITS_MIN. AVR's use of TARGET_PAGE_BITS == 8 is unfortunately too small. This was due to having mmio in the first 256 or 512 bytes and RAM starting immediately afterward -- the softmmu page table mapping really doesn't like mixed i/o and sram on the same page. For v2, my solution is to map the balance of the first page with a ram device instead of normal ram. This way, the entire first page is always i/o. In addition, add some symbolic names for the cpu registers in i/o 0x38-0x3f. r~ Richard Henderson (11): target/avr: Fix buffer read in avr_print_insn target/avr: Improve decode of LDS, STS hw/core/cpu: Use size_t for memory_rw_debug len argument target/avr: Remove OFFSET_CPU_REGISTERS target/avr: Remove NUMBER_OF_IO_REGISTERS target/avr: Add defines for i/o port registers target/avr: Move cpu register accesses into system memory target/avr: Use cpu_stb_mmuidx_ra in helper_fullwr target/avr: Use do_stb in avr_cpu_do_interrupt hw/avr: Prepare for TARGET_PAGE_SIZE > 256 target/avr: Increase TARGET_PAGE_BITS to 10 hw/avr/atmega.h | 1 + include/hw/core/cpu.h | 2 +- target/avr/cpu-param.h | 8 +- target/avr/cpu.h | 21 ++- target/avr/helper.h | 3 - target/sparc/cpu.h | 2 +- hw/avr/atmega.c | 39 +++++- target/avr/cpu.c | 16 +++ target/avr/disas.c | 21 ++- target/avr/helper.c | 262 ++++++++++++++++---------------------- target/avr/translate.c | 44 ++++--- target/sparc/mmu_helper.c | 2 +- target/avr/insn.decode | 7 +- 13 files changed, 222 insertions(+), 206 deletions(-)