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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22781209ff3sm54075165ad.257.2025.03.23.10.37.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 10:37:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mrolnik@gmail.com, philmd@linaro.org, pierrick.bouvier@linaro.org Subject: [PATCH 00/17] target/avr: Increase page size Date: Sun, 23 Mar 2025 10:37:12 -0700 Message-ID: <20250323173730.3213964-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For single-binary, we would really like to have a common TARGET_PAGE_BITS_MIN. A value of 10 will suffice for armv4 and will just fit required page flags and alignment. AVR's use of TARGET_PAGE_BITS == 8 is unfortunate, and is due to having memory mapped i/o in the first 256 or 512 bytes and sram starting immediately afterward -- the softmmu page table mapping really doesn't like mixed i/o and sram on the same page. My solution is to bias the entire AVR address space up in the QEMU address space. This places sram at the start of the second QEMU page, and the i/o immediately beforehand, at the end of the first QEMU page. Once the bias exists, we can choose any value we like. Use this to select a larger page size, based on the size of sram. This minimizes the number of pages required to span flash and sram. There are also two bugs fixed in the avr disassembler. r~ Richard Henderson (17): hw/core/cpu: Use size_t for memory_rw_debug len argument target/avr: Fix buffer read in avr_print_insn target/avr: Improve decode of LDS, STS target/avr: Remove OFFSET_CPU_REGISTERS target/avr: Move cpu register accesses into system memory target/avr: Use cpu_stb_mmuidx_ra in helper_fullwr target/avr: Use do_stb in avr_cpu_do_interrupt target/avr: Add offset-io cpu property target/avr: Introduce gen_data_{load,store}_raw target/avr: Update cpu_sp after push and pop target/avr: Implement CPUState.memory_rw_debug target/avr: Handle offset_io in helper.c target/avr: Handle offset_io in avr_cpu_realizefn hw/avr: Set offset_io and increase page size to 1k hw/avr: Pass mcu_type to class_base_init via .class_data hw/avr: Move AtmegaMcuClass to atmega.h target/avr: Enable TARGET_PAGE_BITS_VARY hw/avr/atmega.h | 20 +++ include/hw/core/cpu.h | 2 +- target/avr/cpu-param.h | 13 +- target/avr/cpu.h | 11 +- target/avr/helper.h | 3 - target/sparc/cpu.h | 2 +- hw/avr/arduino.c | 31 ++++- hw/avr/atmega.c | 76 ++++++----- target/avr/cpu.c | 49 +++++++ target/avr/disas.c | 21 ++- target/avr/helper.c | 263 +++++++++++++++++--------------------- target/avr/translate.c | 106 +++++++++------ target/sparc/mmu_helper.c | 2 +- target/avr/insn.decode | 7 +- 14 files changed, 346 insertions(+), 260 deletions(-)