From patchwork Thu Jan 2 18:05:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 854665 Delivered-To: patch@linaro.org Received: by 2002:a5d:4888:0:b0:385:e875:8a9e with SMTP id g8csp7901077wrq; Thu, 2 Jan 2025 10:07:38 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXUa2hPtstbmaRL5qjiPoTIFu4BLn0NGrmzkXLjmWxB+JpzLlQ2kOrfmN8cxIZU4ZCCYYUHHg==@linaro.org X-Google-Smtp-Source: AGHT+IGEqv+Vv10wmbncVvR44OfTzW+9hg/x5wGBdEkEBmpM7zyXHeVszmRuEX2K6UqCXW9amNQn X-Received: by 2002:a05:620a:1711:b0:7b1:1fdd:d54f with SMTP id af79cd13be357-7b9aaad577dmr8256340385a.29.1735841258243; Thu, 02 Jan 2025 10:07:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1735841258; cv=none; d=google.com; s=arc-20240605; b=isVV1ORjBO3PRpO1POZqAkqVWVJPSvAjNtU+qM7hOkhwA5NK3n3nAV1NXqjR1bo8Ay 18Jfq/MT67C4V14XiJ8f1Rcg876omNDfCRhoLx9ylqF87rzOlEqcTJ2I+IwKSiw5KJ/+ Adst0GgUIP/sJat5MkI6xsuIYhF87lG5t6hidN93GA2fC+M7wRSWbM5jXZU3OOkGZAd9 H5bdBuXaPr677SEhAzMsJaJdYfrsOf2QpIOwp00hAD/BXvFCQhg9JVBPo8dj3/HZ5eiD gxQL3d4mUJ0uOZJOx7y2i1w2qR9IxvHObnoxfO29OGzopyZa+gkRN6cQoun6bLuHEm7m spiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:to:from:dkim-signature; bh=272K03IG9fFwpfNqUsDhlxebfJi0GyPACpBEPh/+9UU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=F5vs+3dZ5EJnKUuFaE3BcP4rtgRAi+4YdIhnmLV37KK32AHB9ffdbBa2c8yK5TQsxC tnJS2rBc/Vh5NBay9zr0jmkm2PPDowOLxOAtwAFPba3B6TK1aPoHQsEp0ZXWFOwBIRHr IFFhjV5mAPYxXbothsQumxhjbXfs9EEgF++zc0XpJYA12ZqgN5wFwmwyYGuPDQjHAq54 u2aEZwvO7KSPnM0jFRwlARbSnXda4BUqKcTrbOnwy1wQC+7tDzDj0bbu57s7AMq/HE9N Qoomog8TulG9aJblWi3sXl9nczda6gE/MGtrzlKL/DtPxD8TalyCfIZy4q3tvoMJ8yXX dPug==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sam0QAze; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-46a3ebc5660si329820861cf.493.2025.01.02.10.07.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 02 Jan 2025 10:07:38 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sam0QAze; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tTPb7-0006wL-Vr; Thu, 02 Jan 2025 13:07:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tTPb2-0006vj-7H for qemu-devel@nongnu.org; Thu, 02 Jan 2025 13:07:00 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tTPaz-00056t-GF for qemu-devel@nongnu.org; Thu, 02 Jan 2025 13:06:59 -0500 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-21631789fcdso118432865ad.1 for ; Thu, 02 Jan 2025 10:06:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1735841216; x=1736446016; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=272K03IG9fFwpfNqUsDhlxebfJi0GyPACpBEPh/+9UU=; b=Sam0QAzeYGyRnOu6yrCLp4FnlCQHHSNgak3OT3ECDe5AbqlmqziVm/eNnzURomX2hj H5kx+vz0QD7Pp8wMv9Ow7ManyhlJYOYhm83HKuUgu5lw16lHXs00GrGE4/96Tigakaen vv18+2ykJxm9nsq+fgI6WjpQCURL1BtvKc+99P+SarjvaSmzjNnc/hcXT/q+u8tk28at lD5V4W5E9jNT8RbeCdtBoERZxC3QSrERO5Pae49a5L6qCB2SRg3Lkjhr4FOMDk/hHIKu mqQSf/YruIlW6jlI++P3GfUJoiySaX5YuwVxjXDQc24BfoqIyo4uPCY7gvc/ti8auzfN LotQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735841216; x=1736446016; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=272K03IG9fFwpfNqUsDhlxebfJi0GyPACpBEPh/+9UU=; b=MSgYD2vlm6LQaRNB7ct0+aWmfopGsPohoNDpRl5C9CeGwXwtX1etuCrz0O9v9YllrY saNMbQbUSPOvTLGGU5yqxIFQc2zyFdSEESDW83t9tc5nmOqokkmcn+df9h7spKhUftua 5+9Hw6dtXvXIbP34C5plBNyL8YpvvPYBSvTrJRM8gcSA8lM/kyPZ0SQPljHqIcsIS8sh 12pS3uC2L+sdBEF759NE+4cul1uY4thZtPrm9cYkrmjfMFU8P+xsLtWZoTu9q5rCqSLd 70qC4GUa+HxoUMIZz6liW2ArkJ/muDTV9melKwjp77WcLQxWfSiwHyY73a6cS2zGyjRz swzg== X-Gm-Message-State: AOJu0YwZJrqoN1F++zULmL47OOXoZbGvZfxlwiPFCxhjBz53+pG8NLAv Bkz/itnuSAuocTG/5tcAyBKS4yPveU5xQjgA2g63QO9ghvEaHQ1KtaA+94fRAh8bnFg88N52zui K X-Gm-Gg: ASbGncs6m/Yk+47UguCedCK+P89vlkh7BArMnEM2NCyH96x5Ynr06BS1HYZN6B/njth GzHennwLkPNI/jnmVy7a+aS0EzwgC1nc09HNjx/ljEqxg39Bs8YLU03RLPUm9Fbzl5FEBerlN/p 7oHPy26QNHbOLvwa7ycTFZu0cJ0Dzt3nu2kRu++KKZCet5Kbk1LOE32U4D4Jr5F+BQ618vMD/bH pk6gyBWByKw5obT8my2RQ72GsE9eZVyRsh3G5DTpKfYBsvdz2VPwOxwnUn/+w== X-Received: by 2002:a05:6a20:6a0d:b0:1e1:a920:225d with SMTP id adf61e73a8af0-1e5e1fa207dmr72040084637.19.1735841215642; Thu, 02 Jan 2025 10:06:55 -0800 (PST) Received: from stoup.. ([63.239.63.212]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72ad3393d5fsm20604456b3a.154.2025.01.02.10.06.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jan 2025 10:06:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 00/73] tcg: Merge *_i32 and *_i64 opcodes Date: Thu, 2 Jan 2025 10:05:40 -0800 Message-ID: <20250102180654.1420056-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently we have individual opcodes for each integer type. This makes things difficult in tcg/optimize.c when we want to transform the opcode stream. Add a TCGType field to TCGOp and use that instead. Merge all of the opcodes that are common to both TCG_TYPE_I32 and TCG_TYPE_I64. We could eventually merge some of the vector opcodes too, but since those have an additional element size operand, that is a larger job. This also moves quite a lot of the tcg backend implementation out of the publicly exposed headers. After this patchset is complete, we will not rebuild target translators for most changes to the tcg backend. r~ Richard Henderson (73): tcg: Add TCGOp.type tcg: Add TCGHelperInfo.out_type tcg: Add TCGType argument to tcg_emit_op, tcg_op_insert_* tcg: Add TCGType argument to tcg_gen_op* tcg: Remove TCGOP_VECL tcg: Move call abi parameters from tcg-target.h to tcg-target.c.inc tcg: Add TCGType argument to tcg_op_supported target/arm: Do not test TCG_TARGET_HAS_bitsel_vec target/arm: Use tcg_op_supported target/tricore: Use tcg_op_supported tcg: Add tcg_op_deposit_valid target/i386: Remove TCG_TARGET_extract_tl_valid target/i386: Use tcg_op_deposit_valid target/i386: Use tcg_op_supported tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELS tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc tcg/tci: Move TCI specific opcodes to tcg-target-opc.h.inc tcg: Move fallback tcg_can_emit_vec_op out of line tcg: Split out tcg-target-has.h and tcg-has.h tcg: Split out tcg-target-mo.h tcg: Merge TCG_TARGET_HAS_{div,rem,div2} tcg: Merge TCG_TARGET_HAS_{andc,orc,nand,nor,eqv,not} tcg/mips: Expand bswap unconditionally tcg: Merge TCG_TARGET_HAS_bswap* tcg: Merge TCG_TARGET_HAS_rot_{i32,i64} tcg: Merge TCG_TARGET_HAS_{clz,ctz,ctpop} tcg: Merge TCG_TARGET_HAS_{muls2,mulu2,mulsh,muluh} tcg: Merge TCG_TARGET_HAS_{add2,sub2} tcg: Merge TCG_TARGET_HAS_negsetcond_{i32,i64} tcg/i386: Handle all 8-bit extensions for i686 tcg/i386: Fold the ext{8,16,32}[us] cases into {s}extract tcg/aarch64: Provide TCG_TARGET_{s}extract_valid tcg/aarch64: Expand extract with offset 0 with andi tcg/arm: Add full [US]XT[BH] into {s}extract tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extract tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extract tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extract tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extract tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extract tcg/sparc64: Use SRA, SRL for {s}extract_i64 tcg/tci: Provide TCG_TARGET_{s}extract_valid tcg/tci: Remove assertions for deposit and extract tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64} tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64} tcg: Merge TCG_TARGET_HAS_extract2_{i32,i64} tcg: Make INDEX_op_extrh_i64_i32 mandatory tcg: Remove INDEX_op_ext{8,16,32}{us} tcg: Reorg process_op_defs tcg: Remove args_ct from TCGOpDef tcg: Constify tcg_op_defs tcg: Use tcg_op_supported in process_op_defs tcg: Use C_NotImplemented in tcg_target_op_def tcg: Pass TCGOp to tcg_target_op_def tcg: Merge INDEX_op_{ld,st}*_{i32_i64} tcg: Remove INDEX_op_qemu_st8_*_i32 tcg: Add TCGType argument to tcg_out_op tcg/optimize: Remove OptContext.type tcg: Remove TCG_OPF_64BIT tcg: Change have_vec to has_type in tcg_op_supported tcg: Merge INDEX_op_mov_{i32,i64} tcg: Merge integer logical operations tcg: Merge integer add, sub, neg operations tcg: Merge integer add2, sub2 operations tcg: Merge integer mul, div operations tcg: Merge brcond, setcond, negsetcond, movcond operations tcg: Merge extract, sextract operations tcg: Merge integer shift operations tcg: Merge deposit operations tcg: Merge extract2 operations tcg: Merge host integer load/store operations tcg: Merge bswap operations tcg: Merge clz, ctz, ctpop operations accel/tcg/internal-target.h | 1 + include/tcg/helper-info.h | 3 +- include/tcg/tcg-op.h | 8 +- include/tcg/tcg-opc.h | 334 ++--- include/tcg/tcg.h | 144 +- tcg/aarch64/tcg-target-has.h | 76 + tcg/aarch64/tcg-target-mo.h | 12 + tcg/aarch64/tcg-target.h | 126 -- tcg/arm/tcg-target-has.h | 91 ++ tcg/arm/tcg-target-mo.h | 13 + tcg/arm/tcg-target.h | 86 -- tcg/i386/tcg-target-con-str.h | 2 +- tcg/i386/tcg-target-has.h | 124 ++ tcg/i386/tcg-target-mo.h | 19 + tcg/i386/tcg-target.h | 162 -- tcg/loongarch64/tcg-target-has.h | 72 + tcg/loongarch64/tcg-target-mo.h | 12 + tcg/loongarch64/tcg-target.h | 115 -- tcg/mips/tcg-target-has.h | 88 ++ tcg/mips/tcg-target-mo.h | 13 + tcg/mips/tcg-target.h | 130 -- tcg/ppc/tcg-target-has.h | 86 ++ tcg/ppc/tcg-target-mo.h | 12 + tcg/ppc/tcg-target.h | 126 -- tcg/riscv/tcg-target-con-set.h | 2 +- tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target-has.h | 83 ++ tcg/riscv/tcg-target-mo.h | 12 + tcg/riscv/tcg-target.h | 116 -- tcg/s390x/tcg-target-has.h | 96 ++ tcg/s390x/tcg-target-mo.h | 12 + tcg/s390x/tcg-target.h | 126 -- tcg/sparc64/tcg-target-has.h | 51 + tcg/sparc64/tcg-target-mo.h | 12 + tcg/sparc64/tcg-target.h | 91 -- tcg/tcg-has.h | 51 + tcg/tcg-internal.h | 13 +- tcg/tci/tcg-target-has.h | 42 + tcg/tci/tcg-target-mo.h | 17 + tcg/tci/tcg-target.h | 94 -- target/arm/tcg/translate-a64.c | 10 +- target/arm/tcg/translate-sve.c | 22 +- target/arm/tcg/translate.c | 2 +- target/sh4/translate.c | 26 +- target/tricore/translate.c | 4 +- tcg/optimize.c | 813 ++++------ tcg/tcg-common.c | 4 +- tcg/tcg-op-gvec.c | 1 + tcg/tcg-op-ldst.c | 43 +- tcg/tcg-op-vec.c | 49 +- tcg/tcg-op.c | 1310 +++++++---------- tcg/tcg.c | 1099 +++++++------- tcg/tci.c | 551 +++---- docs/devel/tcg-ops.rst | 28 +- target/i386/tcg/emit.c.inc | 20 +- ...{tcg-target.opc.h => tcg-target-opc.h.inc} | 4 +- tcg/aarch64/tcg-target.c.inc | 436 ++---- ...{tcg-target.opc.h => tcg-target-opc.h.inc} | 6 +- tcg/arm/tcg-target.c.inc | 278 ++-- ...{tcg-target.opc.h => tcg-target-opc.h.inc} | 22 +- tcg/i386/tcg-target.c.inc | 502 +++---- ...{tcg-target.opc.h => tcg-target-opc.h.inc} | 0 tcg/loongarch64/tcg-target.c.inc | 601 ++++---- tcg/mips/tcg-target-opc.h.inc | 1 + tcg/mips/tcg-target.c.inc | 641 ++++---- ...{tcg-target.opc.h => tcg-target-opc.h.inc} | 12 +- tcg/ppc/tcg-target.c.inc | 699 ++++----- ...{tcg-target.opc.h => tcg-target-opc.h.inc} | 0 tcg/riscv/tcg-target.c.inc | 624 ++++---- ...{tcg-target.opc.h => tcg-target-opc.h.inc} | 6 +- tcg/s390x/tcg-target.c.inc | 1044 ++++++------- tcg/sparc64/tcg-target-opc.h.inc | 1 + tcg/sparc64/tcg-target.c.inc | 422 +++--- tcg/tcg-ldst.c.inc | 65 - tcg/tcg-pool.c.inc | 162 -- tcg/tci/tcg-target-opc.h.inc | 15 + tcg/tci/tcg-target.c.inc | 511 +++---- 77 files changed, 5541 insertions(+), 7167 deletions(-) create mode 100644 tcg/aarch64/tcg-target-has.h create mode 100644 tcg/aarch64/tcg-target-mo.h create mode 100644 tcg/arm/tcg-target-has.h create mode 100644 tcg/arm/tcg-target-mo.h create mode 100644 tcg/i386/tcg-target-has.h create mode 100644 tcg/i386/tcg-target-mo.h create mode 100644 tcg/loongarch64/tcg-target-has.h create mode 100644 tcg/loongarch64/tcg-target-mo.h create mode 100644 tcg/mips/tcg-target-has.h create mode 100644 tcg/mips/tcg-target-mo.h create mode 100644 tcg/ppc/tcg-target-has.h create mode 100644 tcg/ppc/tcg-target-mo.h create mode 100644 tcg/riscv/tcg-target-has.h create mode 100644 tcg/riscv/tcg-target-mo.h create mode 100644 tcg/s390x/tcg-target-has.h create mode 100644 tcg/s390x/tcg-target-mo.h create mode 100644 tcg/sparc64/tcg-target-has.h create mode 100644 tcg/sparc64/tcg-target-mo.h create mode 100644 tcg/tcg-has.h create mode 100644 tcg/tci/tcg-target-has.h create mode 100644 tcg/tci/tcg-target-mo.h rename tcg/aarch64/{tcg-target.opc.h => tcg-target-opc.h.inc} (82%) rename tcg/arm/{tcg-target.opc.h => tcg-target-opc.h.inc} (75%) rename tcg/i386/{tcg-target.opc.h => tcg-target-opc.h.inc} (72%) rename tcg/loongarch64/{tcg-target.opc.h => tcg-target-opc.h.inc} (100%) create mode 100644 tcg/mips/tcg-target-opc.h.inc rename tcg/ppc/{tcg-target.opc.h => tcg-target-opc.h.inc} (83%) rename tcg/riscv/{tcg-target.opc.h => tcg-target-opc.h.inc} (100%) rename tcg/s390x/{tcg-target.opc.h => tcg-target-opc.h.inc} (75%) create mode 100644 tcg/sparc64/tcg-target-opc.h.inc delete mode 100644 tcg/tcg-ldst.c.inc delete mode 100644 tcg/tcg-pool.c.inc create mode 100644 tcg/tci/tcg-target-opc.h.inc