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[176.184.27.250]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432b0562ccdsm214644345e9.23.2024.11.12.10.10.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Nov 2024 10:10:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Richard Henderson , Peter Maydell , Anton Johansson , Jason Wang , qemu-arm@nongnu.org, =?utf-8?q?Marc-Andr?= =?utf-8?q?=C3=A9_Lureau?= , Thomas Huth , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 00/20] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Date: Tue, 12 Nov 2024 19:10:24 +0100 Message-ID: <20241112181044.92193-1-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is the result of a long discussion with Edgar (started few years ago!) and Paolo: https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f6814b5@redhat.com/ After clarification from Richard on MMIO/RAM accesses, I figured strengthening the model regions would make things obvious, eventually allowing to remove the tswap() calls for good. This costly series mostly plays around with MemoryRegions. The model has a mix of RAM/MMIO in its address range. Currently they are implemented as a MMIO array of u32. Since the core memory layer swaps accesses for MMIO, the device implementation has to swap them back. In order to avoid that, we'll map the RAM regions as RAM MRs. First we move each MMIO register to new MMIO regions (RX and TX). Then what is left are the RAM buffers; we convert them to RAM MRs, removing the need for tswap() at all. Once reviewed, I'll respin my "hw/microblaze: Allow running cross-endian vCPUs" series based on this. Please review, Phil. Philippe Mathieu-Daudé (20): hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit hw/net/xilinx_ethlite: Convert some debug logs to trace events hw/net/xilinx_ethlite: Remove unuseful debug logs hw/net/xilinx_ethlite: Update QOM style hw/net/xilinx_ethlite: Correct maximum RX buffer size hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented) hw/net/xilinx_ethlite: Rename rxbuf -> port_index hw/net/xilinx_ethlite: Add addr_to_port_index() helper hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper hw/net/xilinx_ethlite: Access RX_CTRL register for each port hw/net/xilinx_ethlite: Access TX_GIE register for each port hw/net/xilinx_ethlite: Access TX_LEN register for each port hw/net/xilinx_ethlite: Access TX_CTRL register for each port hw/net/xilinx_ethlite: Map RX_CTRL as MMIO hw/net/xilinx_ethlite: Map TX_LEN as MMIO hw/net/xilinx_ethlite: Map TX_GIE as MMIO hw/net/xilinx_ethlite: Map TX_CTRL as MMIO hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container' hw/char/xilinx_uartlite.c | 4 + hw/intc/xilinx_intc.c | 4 + hw/net/xilinx_ethlite.c | 357 ++++++++++++++++++++++++-------------- hw/timer/xilinx_timer.c | 4 + hw/net/trace-events | 4 + 5 files changed, 246 insertions(+), 127 deletions(-)