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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1396948dsm14351765ad.225.2024.10.05.08.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 08:25:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@kernel.org, peter.maydell@linaro.org, alex.bennee@linaro.org, linux-parisc@vger.kernel.org, qemu-arm@nongnu.org Subject: [PATCH 00/20] accel/tcg: Introduce tlb_fill_align hook Date: Sat, 5 Oct 2024 08:25:31 -0700 Message-ID: <20241005152551.307923-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This new hook will allow targets to recognize an alignment fault with the correct priority with respect to other faults that can be raised by paging. This should fix several hppa fault priority issues, most importantly that access permissions come before alignment. This should fix the documented error in the Arm alignment fault due to memory type. r~ Richard Henderson (20): accel/tcg: Assert noreturn from write-only page for atomics accel/tcg: Expand tlb_fill for 3 callers include/exec/memop: Move get_alignment_bits from tcg.h include/exec/memop: Rename get_alignment_bits include/exec/memop: Introduce memop_atomicity_bits hw/core/tcg-cpu-ops: Introduce tlb_fill_align hook accel/tcg: Use the tlb_fill_align hook target/hppa: Add MemOp argument to hppa_get_physical_address target/hppa: Perform access rights before protection id check target/hppa: Fix priority of T, D, and B page faults target/hppa: Handle alignment faults in hppa_get_physical_address target/hppa: Add hppa_cpu_tlb_fill_align target/arm: Pass MemOp to get_phys_addr target/arm: Pass MemOp to get_phys_addr_with_space_nogpc target/arm: Pass MemOp to get_phys_addr_gpc target/arm: Pass MemOp to get_phys_addr_nogpc target/arm: Pass MemOp through get_phys_addr_twostage target/arm: Pass MemOp to get_phys_addr_lpae target/arm: Move device detection earlier in get_phys_addr_lpae target/arm: Fix alignment fault priority in get_phys_addr_lpae include/exec/memop.h | 47 +++++++++++ include/hw/core/tcg-cpu-ops.h | 25 ++++++ include/tcg/tcg.h | 23 ------ target/arm/internals.h | 6 +- target/hppa/cpu.h | 5 +- accel/tcg/cputlb.c | 142 +++++++++++++++++---------------- accel/tcg/user-exec.c | 4 +- target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/helper.c | 4 +- target/arm/ptw.c | 139 ++++++++++++++++++-------------- target/arm/tcg/cpu-v7m.c | 1 + target/arm/tcg/m_helper.c | 8 +- target/arm/tcg/tlb_helper.c | 2 +- target/arm/tcg/translate-a64.c | 4 +- target/avr/cpu.c | 1 + target/hppa/cpu.c | 1 + target/hppa/int_helper.c | 2 +- target/hppa/mem_helper.c | 50 ++++++++---- target/hppa/op_helper.c | 2 +- target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + target/xtensa/translate.c | 2 +- tcg/tcg-op-ldst.c | 6 +- tcg/tcg.c | 2 +- tcg/arm/tcg-target.c.inc | 4 +- tcg/sparc64/tcg-target.c.inc | 2 +- 39 files changed, 302 insertions(+), 196 deletions(-)