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[176.184.49.210]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7dc9d88650sm137862566b.152.2024.08.02.14.31.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 02 Aug 2024 14:31:24 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: BALATON Zoltan , "Michael S . Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Aurelien Jarno Subject: [PATCH-for-9.1 v5 0/2] hw/pci-host/gt64120: Set PCI base address register write mask Date: Fri, 2 Aug 2024 23:31:20 +0200 Message-ID: <20240802213122.86852-1-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=philmd@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org v5: - correct wmask (Zoltan) v4: - invert patches order - set wmask in DeviceRealize - update patch descriptions (migration, Resettable API) Philippe Mathieu-Daudé (2): hw/pci-host/gt64120: Set PCI base address register write mask hw/pci-host/gt64120: Reset config registers during RESET phase hw/pci-host/gt64120.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)