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[00/17] target/arm: AdvSIMD decodetree conversion, part 4

Message ID 20240717060903.205098-1-richard.henderson@linaro.org
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Series target/arm: AdvSIMD decodetree conversion, part 4 | expand

Message

Richard Henderson July 17, 2024, 6:08 a.m. UTC
Flush before the queue gets too big.
Also, there's a bug fix in patch 14.

r~

Richard Henderson (17):
  target/arm: Use tcg_gen_extract2_i64 for EXT
  target/arm: Convert EXT to decodetree
  target/arm: Convert TBL, TBX to decodetree
  target/arm: Convert UZP, TRN, ZIP to decodetree
  target/arm: Simplify do_reduction_op
  target/arm: Convert ADDV, *ADDLV, *MAXV, *MINV to decodetree
  target/arm: Convert FMAXNMV, FMINNMV, FMAXV, FMINV to decodetree
  target/arm: Convert FMOVI (scalar, immediate) to decodetree
  target/arm: Convert MOVI, FMOV, ORR, BIC (vector immediate) to
    decodetree
  target/arm: Introduce gen_gvec_sshr, gen_gvec_ushr
  target/arm: Fix whitespace near gen_srshr64_i64
  target/arm: Convert handle_vec_simd_shri to decodetree
  target/arm: Convet handle_vec_simd_shli to decodetree
  target/arm: Clear high SVE elements in handle_vec_simd_wshli
  target/arm: Use {,s}extract in handle_vec_simd_wshli
  target/arm: Convert SSHLL, USHLL to decodetree
  target/arm: Push tcg_rnd into handle_shri_with_rndacc

 target/arm/tcg/translate.h      |    5 +
 target/arm/tcg/gengvec.c        |   21 +-
 target/arm/tcg/translate-a64.c  | 1123 +++++++++++--------------------
 target/arm/tcg/translate-neon.c |   25 +-
 target/arm/tcg/a64.decode       |   87 +++
 5 files changed, 520 insertions(+), 741 deletions(-)

Comments

Michael Tokarev Aug. 11, 2024, 5:40 p.m. UTC | #1
17.07.2024 09:08, Richard Henderson wrote:
> Flush before the queue gets too big.
> Also, there's a bug fix in patch 14.

Hi!

Has this patchset (together with the bugfix) been forgotten?
Maybe we should include at least the bug fix for 9.1?

Thanks,

/mjt

> r~
> 
> Richard Henderson (17):
>    target/arm: Use tcg_gen_extract2_i64 for EXT
>    target/arm: Convert EXT to decodetree
>    target/arm: Convert TBL, TBX to decodetree
>    target/arm: Convert UZP, TRN, ZIP to decodetree
>    target/arm: Simplify do_reduction_op
>    target/arm: Convert ADDV, *ADDLV, *MAXV, *MINV to decodetree
>    target/arm: Convert FMAXNMV, FMINNMV, FMAXV, FMINV to decodetree
>    target/arm: Convert FMOVI (scalar, immediate) to decodetree
>    target/arm: Convert MOVI, FMOV, ORR, BIC (vector immediate) to
>      decodetree
>    target/arm: Introduce gen_gvec_sshr, gen_gvec_ushr
>    target/arm: Fix whitespace near gen_srshr64_i64
>    target/arm: Convert handle_vec_simd_shri to decodetree
>    target/arm: Convet handle_vec_simd_shli to decodetree
>    target/arm: Clear high SVE elements in handle_vec_simd_wshli
>    target/arm: Use {,s}extract in handle_vec_simd_wshli
>    target/arm: Convert SSHLL, USHLL to decodetree
>    target/arm: Push tcg_rnd into handle_shri_with_rndacc
> 
>   target/arm/tcg/translate.h      |    5 +
>   target/arm/tcg/gengvec.c        |   21 +-
>   target/arm/tcg/translate-a64.c  | 1123 +++++++++++--------------------
>   target/arm/tcg/translate-neon.c |   25 +-
>   target/arm/tcg/a64.decode       |   87 +++
>   5 files changed, 520 insertions(+), 741 deletions(-)
>
Peter Maydell Aug. 12, 2024, 2:11 p.m. UTC | #2
On Sun, 11 Aug 2024 at 18:41, Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> 17.07.2024 09:08, Richard Henderson wrote:
> > Flush before the queue gets too big.
> > Also, there's a bug fix in patch 14.
>
> Hi!
>
> Has this patchset (together with the bugfix) been forgotten?
> Maybe we should include at least the bug fix for 9.1?

Thanks for the ping -- I had indeed lost track of the
patchset. The series itself is not 9.1 material, but
the bugfix could go in. (I don't rate the bugfix as
very critical -- nobody's noticed it in the at least
five years it's been there.)

-- PMM
Peter Maydell Aug. 12, 2024, 3:14 p.m. UTC | #3
On Wed, 17 Jul 2024 at 07:09, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Flush before the queue gets too big.
> Also, there's a bug fix in patch 14.
>
> r~
>
> Richard Henderson (17):
>   target/arm: Use tcg_gen_extract2_i64 for EXT
>   target/arm: Convert EXT to decodetree
>   target/arm: Convert TBL, TBX to decodetree
>   target/arm: Convert UZP, TRN, ZIP to decodetree
>   target/arm: Simplify do_reduction_op
>   target/arm: Convert ADDV, *ADDLV, *MAXV, *MINV to decodetree
>   target/arm: Convert FMAXNMV, FMINNMV, FMAXV, FMINV to decodetree
>   target/arm: Convert FMOVI (scalar, immediate) to decodetree
>   target/arm: Convert MOVI, FMOV, ORR, BIC (vector immediate) to
>     decodetree
>   target/arm: Introduce gen_gvec_sshr, gen_gvec_ushr
>   target/arm: Fix whitespace near gen_srshr64_i64
>   target/arm: Convert handle_vec_simd_shri to decodetree
>   target/arm: Convet handle_vec_simd_shli to decodetree
>   target/arm: Clear high SVE elements in handle_vec_simd_wshli
>   target/arm: Use {,s}extract in handle_vec_simd_wshli
>   target/arm: Convert SSHLL, USHLL to decodetree
>   target/arm: Push tcg_rnd into handle_shri_with_rndacc

Other than the need-to-avoid-shift-by-negative nits in
patches 12 and 13, whole series

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM