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[174.21.76.141]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b438f5679sm2687280b3a.90.2024.07.09.20.28.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 20:28:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, balaton@eik.bme.hu, max.chou@sifive.com Subject: [PATCH v2 00/13] Fixes for user-only munmap races Date: Tue, 9 Jul 2024 20:28:01 -0700 Message-ID: <20240710032814.104643-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Supercedes: 20240702234155.2106399-1-richard.henderson@linaro.org ("[PATCH 0/2] target/arm: Fix unwind from dc zva and FEAT_MOPS") Supercedes: 20240702234659.2106870-1-richard.henderson@linaro.org ("[PATCH 0/4] target/ppc: Cleanups for dcbz") After looking at the first dc zva patch set again, I can see no difference between the memset used by dc dva and the plain memory accesses used by SVE and SME. In all cases it's a host memory access that might fault even after probe_access, due to a race. So I've dropped memset_ra and memmove_ra, and instead expose the basic set/clear_helper_retaddr interface. This allows one set/clear to cover entire loops, instead of trebling the overhead of each individual access. I've included the ppc dcbz cleanups, so that the final improvement applies cleanly. I've updated s390x, though it isn't as clean as I would like. I've tidied the riscv use of tlb_vaddr_to_host, which Peter noticed. The usage was incorrect in general. There is no race condition here because it still uses cpu_ld*_data_ra in the end and not a bare host memory access. But the ongoing work to improve riscv vector memory instructions should take note. r~ BALATON Zoltan (1): target/ppc/mem_helper.c: Remove a conditional from dcbz_common() Richard Henderson (12): accel/tcg: Move {set,clear}_helper_retaddr to cpu_ldst.h target/arm: Use cpu_env in cpu_untagged_addr target/arm: Use set/clear_helper_retaddr in helper-a64.c target/arm: Use set/clear_helper_retaddr in SVE and SME helpers target/ppc: Hoist dcbz_size out of dcbz_common target/ppc: Split out helper_dbczl for 970 target/ppc: Merge helper_{dcbz,dcbzep} target/ppc: Improve helper_dcbz for user-only target/s390x: Use user_or_likely in do_access_memset target/s390x: Use user_or_likely in access_memmove target/s390x: Use set/clear_helper_retaddr in mem_helper.c target/riscv: Simplify probing in vext_ldff accel/tcg/user-retaddr.h | 28 --------- include/exec/cpu_ldst.h | 34 +++++++++++ target/arm/cpu.h | 4 +- target/ppc/helper.h | 6 +- accel/tcg/cpu-exec.c | 3 - accel/tcg/user-exec.c | 1 - target/arm/tcg/helper-a64.c | 14 ++++- target/arm/tcg/sme_helper.c | 16 ++++++ target/arm/tcg/sve_helper.c | 26 +++++++++ target/ppc/mem_helper.c | 51 +++++++++-------- target/ppc/translate.c | 24 ++++---- target/riscv/vector_helper.c | 34 +++++------ target/s390x/tcg/mem_helper.c | 103 +++++++++++++++++++++------------- 13 files changed, 219 insertions(+), 125 deletions(-) delete mode 100644 accel/tcg/user-retaddr.h