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[RESEND,0/6] target/arm: AdvSIMD decodetree conversion, part 3

Message ID 20240709000610.382391-1-richard.henderson@linaro.org
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Series target/arm: AdvSIMD decodetree conversion, part 3 | expand

Message

Richard Henderson July 9, 2024, 12:06 a.m. UTC 
[Sorry about the @qemu.prg typo; resend for anyone replying.]

A small set, but better than waiting for a larger set.
It's a good stopping point, finishing the convertion of

  disas_simd_three_reg_diff
  disas_simd_scalar_three_reg_diff
  disas_simd_indexed


r~


Richard Henderson (6):
  target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to
    decodetree
  target/arm: Convert SADDL, SSUBL, SABDL, SABAL, and unsigned to
    decodetree
  target/arm: Convert SQDMULL, SQDMLAL, SQDMLSL to decodetree
  target/arm: Convert SADDW, SSUBW, UADDW, USUBW to decodetree
  target/arm: Convert ADDHN, SUBHN, RADDHN, RSUBHN to decodetree
  target/arm: Convert PMULL to decodetree

 target/arm/tcg/translate-a64.c | 1155 +++++++++++---------------------
 target/arm/tcg/a64.decode      |   77 +++
 2 files changed, 460 insertions(+), 772 deletions(-)

Comments

Peter Maydell July 11, 2024, 10:06 a.m. UTC | #1 
On Tue, 9 Jul 2024 at 01:06, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> [Sorry about the @qemu.prg typo; resend for anyone replying.]
>
> A small set, but better than waiting for a larger set.
> It's a good stopping point, finishing the convertion of
>
>   disas_simd_three_reg_diff
>   disas_simd_scalar_three_reg_diff
>   disas_simd_indexed
>
>
> r~
>
>
> Richard Henderson (6):
>   target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to
>     decodetree
>   target/arm: Convert SADDL, SSUBL, SABDL, SABAL, and unsigned to
>     decodetree
>   target/arm: Convert SQDMULL, SQDMLAL, SQDMLSL to decodetree
>   target/arm: Convert SADDW, SSUBW, UADDW, USUBW to decodetree
>   target/arm: Convert ADDHN, SUBHN, RADDHN, RSUBHN to decodetree
>   target/arm: Convert PMULL to decodetree

Applied to target-arm.next, thanks.

-- PMM