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([149.14.240.163]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42013c5fa61sm132080825e9.40.2024.05.15.08.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 08:08:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, laurent@vivier.eu Subject: [PATCH v3 00/28] linux-user/i386: Properly align signal frame Date: Wed, 15 May 2024 17:08:09 +0200 Message-Id: <20240515150837.259747-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org v2: https://lore.kernel.org/qemu-devel/20240409050302.1523277-1-richard.henderson@linaro.org/ Disconnect fpstate from sigframe, just like the kernel does. Return the separate portions of the frame from get_sigframe. Alter all of the target fpu routines to access memory that has already been translated and sized. Changes for v3: - Address review issues (bonzini). - Rebase. Patches needing review: 02-target-i386-Convert-do_fldt-do_fstt-to-X86Access.patch 19-linux-user-i386-Fix-mregparm-3-for-signal-deliver.patch 23-target-i386-Honor-xfeatures-in-xrstor_sigcontext.patch r~ Richard Henderson (28): target/i386: Add tcg/access.[ch] target/i386: Convert do_fldt, do_fstt to X86Access target/i386: Convert helper_{fbld,fbst}_ST0 to X86Access target/i386: Convert do_fldenv to X86Access target/i386: Convert do_fstenv to X86Access target/i386: Convert do_fsave, do_frstor to X86Access target/i386: Convert do_xsave_{fpu,mxcr,sse} to X86Access target/i386: Convert do_xrstor_{fpu,mxcr,sse} to X86Access tagret/i386: Convert do_fxsave, do_fxrstor to X86Access target/i386: Convert do_xsave_* to X86Access target/i386: Convert do_xrstor_* to X86Access target/i386: Split out do_xsave_chk target/i386: Add rbfm argument to cpu_x86_{xsave,xrstor} target/i386: Add {hw,sw}_reserved to X86LegacyXSaveArea linux-user/i386: Drop xfeatures_size from sigcontext arithmetic linux-user/i386: Remove xfeatures from target_fpstate_fxsave linux-user/i386: Replace target_fpstate_fxsave with X86LegacyXSaveArea linux-user/i386: Split out struct target_fregs_state linux-user/i386: Fix -mregparm=3 for signal delivery linux-user/i386: Return boolean success from restore_sigcontext linux-user/i386: Return boolean success from xrstor_sigcontext linux-user/i386: Fix allocation and alignment of fp state target/i386: Honor xfeatures in xrstor_sigcontext target/i386: Convert do_xsave to X86Access target/i386: Convert do_xrstor to X86Access target/i386: Pass host pointer and size to cpu_x86_{fsave,frstor} target/i386: Pass host pointer and size to cpu_x86_{fxsave,fxrstor} target/i386: Pass host pointer and size to cpu_x86_{xsave,xrstor} target/i386/cpu.h | 57 ++- target/i386/tcg/access.h | 40 ++ linux-user/i386/signal.c | 671 ++++++++++++++++++------------- target/i386/tcg/access.c | 169 ++++++++ target/i386/tcg/fpu_helper.c | 561 ++++++++++++++++---------- tests/tcg/x86_64/test-1648.c | 33 ++ target/i386/tcg/meson.build | 1 + tests/tcg/x86_64/Makefile.target | 1 + 8 files changed, 1024 insertions(+), 509 deletions(-) create mode 100644 target/i386/tcg/access.h create mode 100644 target/i386/tcg/access.c create mode 100644 tests/tcg/x86_64/test-1648.c