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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u2-20020adfeb42000000b0033b483d1abcsm5158934wrn.53.2024.03.01.10.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 10:32:20 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker Subject: [PATCH 0/8] target/arm: Implement FEAT_ECV (Enhanced Counter Virtualization) Date: Fri, 1 Mar 2024 18:32:11 +0000 Message-Id: <20240301183219.2424889-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This patchset implements the Arm FEAT_ECV architectural feature, which provides: * some new trap bits for hypervisors to trap accesses to various counter and timer registers * support for scaling of the event stream for the guest (which we don't need to implement because our events are always nops) * new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are "self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning that no barriers are needed around their accesses. For us these are just the same as the normal views, because all our sysregs are inherently self-sychronizing. * a new register CNTPOFF_EL2, which allows the hypervisor to set an adjustable offset for what the guest sees in the physical timer and counter (similar to the existing CNTVOFF_EL2 for the virtual timer and counter) These patchsets implement support for this and enable them in the 'max' CPU. At the start of the series there's one patch doing some "move things to a better header file" and one bugfix for a "no sensible guest should ever do this" corner case. I'm hoping we can get these reviewed in time to get them in before softfreeze. thanks -- PMM Peter Maydell (8): target/arm: Move some register related defines to internals.h target/arm: Timer _EL02 registers UNDEF for E2H == 0 target/arm: use FIELD macro for CNTHCTL bit definitions target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written target/arm: Implement new FEAT_ECV trap bits target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0 target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling target/arm: Enable FEAT_ECV for 'max' CPU docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 10 ++ target/arm/cpu.h | 129 +---------------------- target/arm/internals.h | 143 +++++++++++++++++++++++++ target/arm/helper.c | 189 +++++++++++++++++++++++++++++++--- target/arm/tcg/cpu64.c | 1 + target/arm/trace-events | 1 + 7 files changed, 334 insertions(+), 140 deletions(-)