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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y7-20020a056000108700b0033b470a137esm1492932wrw.79.2024.02.06.05.29.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Feb 2024 05:29:32 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 00/13] hw/arm: Implement new machine mps3-an536 (Cortex-R52 MPS3 AN536 FPGA image) Date: Tue, 6 Feb 2024 13:29:18 +0000 Message-Id: <20240206132931.38376-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This patchset implements a new machine type, mps3-an536. This is similar to our existing mps2-* and mps3-* machine types in that it is a model of an FPGA image for the Arm MPS3 development board. It differs from our current machine types in being based around an R-profile CPU, the Cortex-R52, rather than an M-profile CPU. This patchset implements the board support to a similar level as that of our M-profile MPS machine types: most but not all devices are supported. Some minor missing features are documented in the docs patch (and already in mps2.rst where they apply to all boards in this family). If there's demand (specifically from the Xen development use case which is motivating this board model) we can look at adding them. I have tested with the "selftest" binary supplied with the FPGA image, and also with a Linux kernel. (The kernel support for this board is not upstream, but the patches can be found in this lakml thread https://lore.kernel.org/all/20220630083641.21835-1-vladimir.murzin@arm.com/ or at the git branch https://gitlab.arm.com/linux-arm/linux-vm/-/tree/staging/rclass-5.19 ) To get some of this guest code to boot I had to make some improvements to our Cortex-R52 emulation; these are in the first four patches. thanks -- PMM Peter Maydell (13): target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs target/arm: The Cortex-R52 has a read-only CBAR target/arm: Add Cortex-R52 IMPDEF sysregs target/arm: Allow access to SPSR_hyp from hyp mode hw/misc/mps2-scc: Fix condition for CFG3 register hw/misc/mps2-scc: Factor out which-board conditionals hw/misc/mps2-scc: Make changes needed for AN536 FPGA image hw/arm/mps3r: Initial skeleton for mps3-an536 board hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM hw/arm/mps3r: Add UARTs hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices hw/arm/mps3r: Add remaining devices docs: Add documentation for the mps3-an536 board MAINTAINERS | 3 +- docs/system/arm/mps2.rst | 37 +- configs/devices/arm-softmmu/default.mak | 1 + include/hw/misc/mps2-scc.h | 1 + hw/arm/mps3r.c | 640 ++++++++++++++++++++++++ hw/misc/mps2-scc.c | 138 ++++- target/arm/helper.c | 2 +- target/arm/tcg/cpu32.c | 109 ++++ target/arm/tcg/op_helper.c | 43 +- target/arm/tcg/translate.c | 19 +- hw/arm/Kconfig | 5 + hw/arm/meson.build | 1 + 12 files changed, 955 insertions(+), 44 deletions(-) create mode 100644 hw/arm/mps3r.c