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[176.172.55.165]) by smtp.gmail.com with ESMTPSA id s10-20020a05600c45ca00b00407752f5ab6sm12592013wmo.6.2023.10.24.09.24.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 24 Oct 2023 09:24:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Joel Stanley , Peter Maydell , Andrew Jeffery , qemu-arm@nongnu.org, =?utf-8?q?C=C3=A9dri?= =?utf-8?q?c_Le_Goater?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 00/11] hw/arm/aspeed: Split AspeedSoCState per 2400/2600/10x0 Date: Tue, 24 Oct 2023 18:24:11 +0200 Message-ID: <20231024162423.40206-1-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Hi, This series is extracted for a bigger work. Cortex-A MP clusters (TYPE_A15MPCORE_PRIV) should create the ARM cores in its own state. Unfortunately we don't do it that way, and this model calls qemu_get_cpu(). In order to remove the qemu_get_cpu() call there, we first need to rework some SoC users. This series rework the Aspeed SoC state, so it is clear what fields are really used by a SoC type (2400 / 2600 / 10x0). It will then be easier to have the MP cluster create the core instances. Regards, Phil. Philippe Mathieu-Daudé (11): hw/arm/aspeed: Extract code common to all boards to a common file hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState include/hw/arm/aspeed_soc.h | 35 +++- hw/arm/aspeed.c | 101 +++++------ hw/arm/aspeed_ast10x0.c | 53 +++--- hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 201 +++++----------------- hw/arm/aspeed_ast2600.c | 75 ++++---- hw/arm/aspeed_soc_common.c | 154 +++++++++++++++++ hw/arm/fby35.c | 27 +-- hw/arm/meson.build | 3 +- 8 files changed, 364 insertions(+), 285 deletions(-) rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (76%) create mode 100644 hw/arm/aspeed_soc_common.c