| Message ID | 20231022060031.490251-1-richard.henderson@linaro.org |
|---|---|
| Headers | show |
| Series | target/sparc: Convert to decodetree | expand |
On 22/10/2023 06:59, Richard Henderson wrote: > Changes for v4: > * Implement htstate for RDHPR, WRHPR. > This was the issue with sun4v rom, "wrhpr %g0, %htstate". > Previously we "implemented" this with nop. But since we > have env->htstate[], add the obvious implementation. Ah I see. So presumably the patch that implements this could also have a Fixes: https://gitlab.com/qemu-project/qemu/-/issues/847 tag? > * The fp asi reorg got lost with "sizes", one of which was for > the size of the access, and the other was a proxy for the > original instruction. This broke "stda reg, [addr] #ASI_FL8_P", > used in Mark's netbsd image. I found a build failure when building this series with --target-list='sparc-softmmu sparc64-softmmu': cc -m64 -mcx16 -Ilibqemu-sparc-softmmu.fa.p -I. -I.. -Itarget/sparc -I../target/sparc -Iqapi -Itrace -Iui -Iui/shader -I/usr/include/pixman-1 -I/usr/include/spice-server -I/usr/include/spice-1 -I/usr/include/glib-2.0 -I/usr/lib/x86_64-linux-gnu/glib-2.0/include -fdiagnostics-color=auto -Wall -Winvalid-pch -Werror -std=gnu11 -O2 -g -fstack-protector-strong -Wundef -Wwrite-strings -Wmissing-prototypes -Wstrict-prototypes -Wredundant-decls -Wold-style-declaration -Wold-style-definition -Wtype-limits -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wempty-body -Wnested-externs -Wendif-labels -Wexpansion-to-defined -Wimplicit-fallthrough=2 -Wmissing-format-attribute -Wno-missing-include-dirs -Wno-shift-negative-value -Wno-psabi -isystem /home/build/src/qemu/git/qemu/linux-headers -isystem linux-headers -iquote . -iquote /home/build/src/qemu/git/qemu -iquote /home/build/src/qemu/git/qemu/include -iquote /home/build/src/qemu/git/qemu/host/include/x86_64 -iquote /home/build/src/qemu/git/qemu/host/include/generic -iquote /home/build/src/qemu/git/qemu/tcg/i386 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -fno-strict-aliasing -fno-common -fwrapv -fPIE -isystem../linux-headers -isystemlinux-headers -DNEED_CPU_H '-DCONFIG_TARGET="sparc-softmmu-config-target.h"' '-DCONFIG_DEVICES="sparc-softmmu-config-devices.h"' -MD -MQ libqemu-sparc-softmmu.fa.p/target_sparc_translate.c.o -MF libqemu-sparc-softmmu.fa.p/target_sparc_translate.c.o.d -o libqemu-sparc-softmmu.fa.p/target_sparc_translate.c.o -c ../target/sparc/translate.c In file included from ../target/sparc/translate.c:21: ../target/sparc/translate.c: In function ‘do_wrhtstate’: /home/build/src/qemu/git/qemu/include/qemu/osdep.h:261:35: error: call to ‘qemu_build_not_reached_always’ declared with attribute error: code path is reachable 261 | #define qemu_build_not_reached() qemu_build_not_reached_always() | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../target/sparc/translate.c:3800:5: note: in expansion of macro ‘qemu_build_not_reached’ 3800 | qemu_build_not_reached(); | ^~~~~~~~~~~~~~~~~~~~~~ [10/23] cc -m64 -mcx16 -Iqemu-io.p The quick diff below was enough to get the build going for me: diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d4468f6673..49b353089e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3797,7 +3797,7 @@ static void do_wrhtstate(DisasContext *dc, TCGv src) tcg_gen_st_i64(src, tp, offsetof(CPUSPARCState, htstate)); #else - qemu_build_not_reached(); + g_assert_not_reached(); #endif } > Changes for v3: > * Relax v8 simm13 checking for Tcc. > * Split gen_op_addx_int and reorganize to not clobber current cc_op. > * Do not replicate decoding for insns that can set cc_op. > > Changes for v2: > * Fixes for JMPL, RETT, SAVE and RESTORE. > * Fixes for FMOV etc, which had lost gen_op_clear_ieee_excp_and_FTT. > * Allow conditional exceptions to be raised out of line > Use this for gen_check_align and conditional trap. > * Keep properties and feature bits in sync. > > > r~ > > > Richard Henderson (90): > target/sparc: Clear may_lookup for npc == DYNAMIC_PC > target/sparc: Implement check_align inline > target/sparc: Avoid helper_raise_exception in helper_st_asi > target/sparc: Set TCG_GUEST_DEFAULT_MO > configs: Enable MTTCG for sparc, sparc64 > target/sparc: Define features via cpu-feature.h.inc > target/sparc: Use CPU_FEATURE_BIT_* for cpu properties > target/sparc: Remove sparcv7 cpu features > target/sparc: Add decodetree infrastructure > target/sparc: Define AM_CHECK for sparc32 > target/sparc: Move CALL to decodetree > target/sparc: Move BPcc and Bicc to decodetree > target/sparc: Move BPr to decodetree > target/sparc: Move FBPfcc and FBfcc to decodetree > target/sparc: Merge gen_cond with only caller > target/sparc: Merge gen_fcond with only caller > target/sparc: Merge gen_branch_[an] with only caller > target/sparc: Pass DisasCompare to advance_jump_cond > target/sparc: Move SETHI to decodetree > target/sparc: Move Tcc to decodetree > target/sparc: Move RDASR, STBAR, MEMBAR to decodetree > target/sparc: Move RDPSR, RDHPR to decodetree > target/sparc: Move RDWIM, RDPR to decodetree > target/sparc: Move RDTBR, FLUSHW to decodetree > target/sparc: Move WRASR to decodetree > target/sparc: Move WRPSR, SAVED, RESTORED to decodetree > target/sparc: Move WRWIM, WRPR to decodetree > target/sparc: Move WRTBR, WRHPR to decodetree > target/sparc: Move basic arithmetic to decodetree > target/sparc: Move ADDC to decodetree > target/sparc: Move MULX to decodetree > target/sparc: Move UMUL, SMUL to decodetree > target/sparc: Move SUBC to decodetree > target/sparc: Move UDIVX, SDIVX to decodetree > target/sparc: Move UDIV, SDIV to decodetree > target/sparc: Move TADD, TSUB, MULS to decodetree > target/sparc: Move SLL, SRL, SRA to decodetree > target/sparc: Move MOVcc, MOVR to decodetree > target/sparc: Move POPC to decodetree > target/sparc: Convert remaining v8 coproc insns to decodetree > target/sparc: Move JMPL, RETT, RETURN to decodetree > target/sparc: Move FLUSH, SAVE, RESTORE to decodetree > target/sparc: Move DONE, RETRY to decodetree > target/sparc: Split out resolve_asi > target/sparc: Drop ifdef around get_asi and friends > target/sparc: Split out ldst functions with asi pre-computed > target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for GET_ASI_DTWINX > target/sparc: Move simple integer load/store to decodetree > target/sparc: Move asi integer load/store to decodetree > target/sparc: Move LDSTUB, LDSTUBA to decodetree > target/sparc: Move SWAP, SWAPA to decodetree > target/sparc: Move CASA, CASXA to decodetree > target/sparc: Move PREFETCH, PREFETCHA to decodetree > target/sparc: Split out fp ldst functions with asi precomputed > target/sparc: Move simple fp load/store to decodetree > target/sparc: Move asi fp load/store to decodetree > target/sparc: Move LDFSR, STFSR to decodetree > target/sparc: Merge LDFSR, LDXFSR implementations > target/sparc: Move EDGE* to decodetree > target/sparc: Move ARRAY* to decodetree > target/sparc: Move ADDRALIGN* to decodetree > target/sparc: Move BMASK to decodetree > target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree > target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree > target/sparc: Use tcg_gen_vec_{add,sub}* > target/sparc: Move gen_ne_fop_FFF insns to decodetree > target/sparc: Move gen_ne_fop_DDD insns to decodetree > target/sparc: Move PDIST to decodetree > target/sparc: Move gen_gsr_fop_DDD insns to decodetree > target/sparc: Move gen_fop_FF insns to decodetree > target/sparc: Move gen_fop_DD insns to decodetree > target/sparc: Move FSQRTq to decodetree > target/sparc: Move gen_fop_FFF insns to decodetree > target/sparc: Move gen_fop_DDD insns to decodetree > target/sparc: Move gen_fop_QQQ insns to decodetree > target/sparc: Move FSMULD to decodetree > target/sparc: Move FDMULQ to decodetree > target/sparc: Move gen_fop_FD insns to decodetree > target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree > target/sparc: Move FqTOs, FqTOi to decodetree > target/sparc: Move FqTOd, FqTOx to decodetree > target/sparc: Move FiTOq, FsTOq to decodetree > target/sparc: Move FdTOq, FxTOq to decodetree > target/sparc: Move FMOVq, FNEGq, FABSq to decodetree > target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree > target/sparc: Convert FCMP, FCMPE to decodetree > target/sparc: Move FPCMP* to decodetree > target/sparc: Move FPACK16, FPACKFIX to decodetree > target/sparc: Convert FZERO, FONE to decodetree > target/sparc: Remove disas_sparc_legacy > > configs/targets/sparc-softmmu.mak | 1 + > configs/targets/sparc64-softmmu.mak | 1 + > linux-user/sparc/target_syscall.h | 6 +- > target/sparc/cpu.h | 76 +- > target/sparc/helper.h | 16 +- > target/sparc/cpu-feature.h.inc | 14 + > target/sparc/insns.decode | 547 ++ > target/sparc/cpu.c | 41 +- > target/sparc/fop_helper.c | 17 +- > target/sparc/helper.c | 8 - > target/sparc/ldst_helper.c | 17 +- > target/sparc/translate.c | 7115 +++++++++++++-------------- > target/sparc/vis_helper.c | 59 - > target/sparc/meson.build | 3 + > 14 files changed, 4170 insertions(+), 3751 deletions(-) > create mode 100644 target/sparc/cpu-feature.h.inc > create mode 100644 target/sparc/insns.decode Otherwise this version passes all my boot tests so: Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Feel free to take this via tcg-next if it's easier for you, and thanks once again for such a great piece of work :) ATB, Mark.
On 10/22/23 05:44, Mark Cave-Ayland wrote: > On 22/10/2023 06:59, Richard Henderson wrote: > >> Changes for v4: >> * Implement htstate for RDHPR, WRHPR. >> This was the issue with sun4v rom, "wrhpr %g0, %htstate". >> Previously we "implemented" this with nop. But since we >> have env->htstate[], add the obvious implementation. > > Ah I see. So presumably the patch that implements this could also have a Fixes: > https://gitlab.com/qemu-project/qemu/-/issues/847 tag? Yes indeed. I'd forgotten about that one. > >> * The fp asi reorg got lost with "sizes", one of which was for >> the size of the access, and the other was a proxy for the >> original instruction. This broke "stda reg, [addr] #ASI_FL8_P", >> used in Mark's netbsd image. > > I found a build failure when building this series with --target-list='sparc-softmmu > sparc64-softmmu': > > cc -m64 -mcx16 -Ilibqemu-sparc-softmmu.fa.p -I. -I.. -Itarget/sparc -I../target/sparc > -Iqapi -Itrace -Iui -Iui/shader -I/usr/include/pixman-1 -I/usr/include/spice-server > -I/usr/include/spice-1 -I/usr/include/glib-2.0 > -I/usr/lib/x86_64-linux-gnu/glib-2.0/include -fdiagnostics-color=auto -Wall -Winvalid-pch > -Werror -std=gnu11 -O2 -g -fstack-protector-strong -Wundef -Wwrite-strings > -Wmissing-prototypes -Wstrict-prototypes -Wredundant-decls -Wold-style-declaration > -Wold-style-definition -Wtype-limits -Wformat-security -Wformat-y2k -Winit-self > -Wignored-qualifiers -Wempty-body -Wnested-externs -Wendif-labels -Wexpansion-to-defined > -Wimplicit-fallthrough=2 -Wmissing-format-attribute -Wno-missing-include-dirs > -Wno-shift-negative-value -Wno-psabi -isystem /home/build/src/qemu/git/qemu/linux-headers > -isystem linux-headers -iquote . -iquote /home/build/src/qemu/git/qemu -iquote > /home/build/src/qemu/git/qemu/include -iquote > /home/build/src/qemu/git/qemu/host/include/x86_64 -iquote > /home/build/src/qemu/git/qemu/host/include/generic -iquote > /home/build/src/qemu/git/qemu/tcg/i386 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 > -D_LARGEFILE_SOURCE -fno-strict-aliasing -fno-common -fwrapv -fPIE > -isystem../linux-headers -isystemlinux-headers -DNEED_CPU_H > '-DCONFIG_TARGET="sparc-softmmu-config-target.h"' > '-DCONFIG_DEVICES="sparc-softmmu-config-devices.h"' -MD -MQ > libqemu-sparc-softmmu.fa.p/target_sparc_translate.c.o -MF > libqemu-sparc-softmmu.fa.p/target_sparc_translate.c.o.d -o > libqemu-sparc-softmmu.fa.p/target_sparc_translate.c.o -c ../target/sparc/translate.c > In file included from ../target/sparc/translate.c:21: > ../target/sparc/translate.c: In function ‘do_wrhtstate’: > /home/build/src/qemu/git/qemu/include/qemu/osdep.h:261:35: error: call to > ‘qemu_build_not_reached_always’ declared with attribute error: code path is reachable > 261 | #define qemu_build_not_reached() qemu_build_not_reached_always() > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > ../target/sparc/translate.c:3800:5: note: in expansion of macro ‘qemu_build_not_reached’ > 3800 | qemu_build_not_reached(); > | ^~~~~~~~~~~~~~~~~~~~~~ > [10/23] cc -m64 -mcx16 -Iqemu-io.p Ho hum, I think I only tested this change with --enable-debug. I'll improve the avail_HYPV() test so the compiler can tell this is a 64-bit thing. > Otherwise this version passes all my boot tests so: > > Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > > Feel free to take this via tcg-next if it's easier for you, and thanks once again for such > a great piece of work :) Thank you for the testing. I can certainly send the PR. r~
Changes for v4: * Implement htstate for RDHPR, WRHPR. This was the issue with sun4v rom, "wrhpr %g0, %htstate". Previously we "implemented" this with nop. But since we have env->htstate[], add the obvious implementation. * The fp asi reorg got lost with "sizes", one of which was for the size of the access, and the other was a proxy for the original instruction. This broke "stda reg, [addr] #ASI_FL8_P", used in Mark's netbsd image. Changes for v3: * Relax v8 simm13 checking for Tcc. * Split gen_op_addx_int and reorganize to not clobber current cc_op. * Do not replicate decoding for insns that can set cc_op. Changes for v2: * Fixes for JMPL, RETT, SAVE and RESTORE. * Fixes for FMOV etc, which had lost gen_op_clear_ieee_excp_and_FTT. * Allow conditional exceptions to be raised out of line Use this for gen_check_align and conditional trap. * Keep properties and feature bits in sync. r~ Richard Henderson (90): target/sparc: Clear may_lookup for npc == DYNAMIC_PC target/sparc: Implement check_align inline target/sparc: Avoid helper_raise_exception in helper_st_asi target/sparc: Set TCG_GUEST_DEFAULT_MO configs: Enable MTTCG for sparc, sparc64 target/sparc: Define features via cpu-feature.h.inc target/sparc: Use CPU_FEATURE_BIT_* for cpu properties target/sparc: Remove sparcv7 cpu features target/sparc: Add decodetree infrastructure target/sparc: Define AM_CHECK for sparc32 target/sparc: Move CALL to decodetree target/sparc: Move BPcc and Bicc to decodetree target/sparc: Move BPr to decodetree target/sparc: Move FBPfcc and FBfcc to decodetree target/sparc: Merge gen_cond with only caller target/sparc: Merge gen_fcond with only caller target/sparc: Merge gen_branch_[an] with only caller target/sparc: Pass DisasCompare to advance_jump_cond target/sparc: Move SETHI to decodetree target/sparc: Move Tcc to decodetree target/sparc: Move RDASR, STBAR, MEMBAR to decodetree target/sparc: Move RDPSR, RDHPR to decodetree target/sparc: Move RDWIM, RDPR to decodetree target/sparc: Move RDTBR, FLUSHW to decodetree target/sparc: Move WRASR to decodetree target/sparc: Move WRPSR, SAVED, RESTORED to decodetree target/sparc: Move WRWIM, WRPR to decodetree target/sparc: Move WRTBR, WRHPR to decodetree target/sparc: Move basic arithmetic to decodetree target/sparc: Move ADDC to decodetree target/sparc: Move MULX to decodetree target/sparc: Move UMUL, SMUL to decodetree target/sparc: Move SUBC to decodetree target/sparc: Move UDIVX, SDIVX to decodetree target/sparc: Move UDIV, SDIV to decodetree target/sparc: Move TADD, TSUB, MULS to decodetree target/sparc: Move SLL, SRL, SRA to decodetree target/sparc: Move MOVcc, MOVR to decodetree target/sparc: Move POPC to decodetree target/sparc: Convert remaining v8 coproc insns to decodetree target/sparc: Move JMPL, RETT, RETURN to decodetree target/sparc: Move FLUSH, SAVE, RESTORE to decodetree target/sparc: Move DONE, RETRY to decodetree target/sparc: Split out resolve_asi target/sparc: Drop ifdef around get_asi and friends target/sparc: Split out ldst functions with asi pre-computed target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for GET_ASI_DTWINX target/sparc: Move simple integer load/store to decodetree target/sparc: Move asi integer load/store to decodetree target/sparc: Move LDSTUB, LDSTUBA to decodetree target/sparc: Move SWAP, SWAPA to decodetree target/sparc: Move CASA, CASXA to decodetree target/sparc: Move PREFETCH, PREFETCHA to decodetree target/sparc: Split out fp ldst functions with asi precomputed target/sparc: Move simple fp load/store to decodetree target/sparc: Move asi fp load/store to decodetree target/sparc: Move LDFSR, STFSR to decodetree target/sparc: Merge LDFSR, LDXFSR implementations target/sparc: Move EDGE* to decodetree target/sparc: Move ARRAY* to decodetree target/sparc: Move ADDRALIGN* to decodetree target/sparc: Move BMASK to decodetree target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree target/sparc: Use tcg_gen_vec_{add,sub}* target/sparc: Move gen_ne_fop_FFF insns to decodetree target/sparc: Move gen_ne_fop_DDD insns to decodetree target/sparc: Move PDIST to decodetree target/sparc: Move gen_gsr_fop_DDD insns to decodetree target/sparc: Move gen_fop_FF insns to decodetree target/sparc: Move gen_fop_DD insns to decodetree target/sparc: Move FSQRTq to decodetree target/sparc: Move gen_fop_FFF insns to decodetree target/sparc: Move gen_fop_DDD insns to decodetree target/sparc: Move gen_fop_QQQ insns to decodetree target/sparc: Move FSMULD to decodetree target/sparc: Move FDMULQ to decodetree target/sparc: Move gen_fop_FD insns to decodetree target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree target/sparc: Move FqTOs, FqTOi to decodetree target/sparc: Move FqTOd, FqTOx to decodetree target/sparc: Move FiTOq, FsTOq to decodetree target/sparc: Move FdTOq, FxTOq to decodetree target/sparc: Move FMOVq, FNEGq, FABSq to decodetree target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree target/sparc: Convert FCMP, FCMPE to decodetree target/sparc: Move FPCMP* to decodetree target/sparc: Move FPACK16, FPACKFIX to decodetree target/sparc: Convert FZERO, FONE to decodetree target/sparc: Remove disas_sparc_legacy configs/targets/sparc-softmmu.mak | 1 + configs/targets/sparc64-softmmu.mak | 1 + linux-user/sparc/target_syscall.h | 6 +- target/sparc/cpu.h | 76 +- target/sparc/helper.h | 16 +- target/sparc/cpu-feature.h.inc | 14 + target/sparc/insns.decode | 547 ++ target/sparc/cpu.c | 41 +- target/sparc/fop_helper.c | 17 +- target/sparc/helper.c | 8 - target/sparc/ldst_helper.c | 17 +- target/sparc/translate.c | 7115 +++++++++++++-------------- target/sparc/vis_helper.c | 59 - target/sparc/meson.build | 3 + 14 files changed, 4170 insertions(+), 3751 deletions(-) create mode 100644 target/sparc/cpu-feature.h.inc create mode 100644 target/sparc/insns.decode