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[176.171.212.97]) by smtp.gmail.com with ESMTPSA id t10-20020a05600c198a00b00403b63e87f2sm2618679wmq.32.2023.10.20.10.00.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 10:00:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Hans-Erik Floryd , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 0/4] stm32f2xx_usart: implement TX interrupts Date: Fri, 20 Oct 2023 19:00:04 +0200 Message-ID: <20231020170009.86870-1-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Hi Hans-Erik, Here is the respin of your patch [*] split in 4 parts for easy reviewing. [*] https://lore.kernel.org/qemu-devel/20231020111428.3260965-1-hans-erik.floryd@rt-labs.com/ Hans-Erik Floryd (4): hw/char/stm32f2xx_usart: Extract common IRQ update code to update_irq() hw/char/stm32f2xx_usart: Update IRQ when SR is read hw/char/stm32f2xx_usart: Update IRQ when DR is written hw/char/stm32f2xx_usart: Add more definitions for CR1 register include/hw/char/stm32f2xx_usart.h | 10 ++++++---- hw/char/stm32f2xx_usart.c | 30 ++++++++++++++++++------------ 2 files changed, 24 insertions(+), 16 deletions(-)