[v2,0/4] stm32f2xx_usart: implement TX interrupts

Message ID	20231020170009.86870-1-philmd@linaro.org
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> To: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>, qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= <marcandre.lureau@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Alistair Francis <alistair@alistair23.me>, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= <philmd@linaro.org> Subject: [PATCH v2 0/4] stm32f2xx_usart: implement TX interrupts Date: Fri, 20 Oct 2023 19:00:04 +0200 Message-ID: <20231020170009.86870-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	stm32f2xx_usart: implement TX interrupts \| expand [v2,0/4] stm32f2xx_usart: implement TX interrupts [v2,1/4] hw/char/stm32f2xx_usart: Extract common IRQ update code to update_irq() [v2,2/4] hw/char/stm32f2xx_usart: Update IRQ when SR is read [v2,3/4] hw/char/stm32f2xx_usart: Update IRQ when DR is written [v2,4/4] hw/char/stm32f2xx_usart: Add more definitions for CR1 register

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20231020170009.86870-1-philmd@linaro.org

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To: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>,
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Subject: [PATCH v2 0/4] stm32f2xx_usart: implement TX interrupts
Date: Fri, 20 Oct 2023 19:00:04 +0200
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Series

stm32f2xx_usart: implement TX interrupts | expand

Message

Philippe Mathieu-Daudé Oct. 20, 2023, 5 p.m. UTC

Hi Hans-Erik,

Here is the respin of your patch [*] split in 4
parts for easy reviewing.

[*] https://lore.kernel.org/qemu-devel/20231020111428.3260965-1-hans-erik.floryd@rt-labs.com/

Hans-Erik Floryd (4):
  hw/char/stm32f2xx_usart: Extract common IRQ update code to
    update_irq()
  hw/char/stm32f2xx_usart: Update IRQ when SR is read
  hw/char/stm32f2xx_usart: Update IRQ when DR is written
  hw/char/stm32f2xx_usart: Add more definitions for CR1 register

 include/hw/char/stm32f2xx_usart.h | 10 ++++++----
 hw/char/stm32f2xx_usart.c         | 30 ++++++++++++++++++------------
 2 files changed, 24 insertions(+), 16 deletions(-)