[v2,00/90] target/sparc: Convert to decodetree

Message ID	20231017061244.681584-1-richard.henderson@linaro.org
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 00/90] target/sparc: Convert to decodetree Date: Mon, 16 Oct 2023 23:11:14 -0700 Message-Id: <20231017061244.681584-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/sparc: Convert to decodetree \| expand [v2,00/90] target/sparc: Convert to decodetree [v2,01/90] target/sparc: Clear may_lookup for npc == DYNAMIC_PC [v2,02/90] target/sparc: Implement check_align inline [v2,03/90] target/sparc: Avoid helper_raise_exception in helper_st_asi [v2,04/90] target/sparc: Set TCG_GUEST_DEFAULT_MO [v2,05/90] configs: Enable MTTCG for sparc, sparc64 [v2,06/90] target/sparc: Define features via cpu-feature.h.inc [v2,07/90] target/sparc: Use CPU_FEATURE_BIT_* for cpu properties [v2,08/90] target/sparc: Remove sparcv7 cpu features [v2,09/90] target/sparc: Add decodetree infrastructure [v2,10/90] target/sparc: Define AM_CHECK for sparc32 [v2,11/90] target/sparc: Move CALL to decodetree [v2,12/90] target/sparc: Move BPcc and Bicc to decodetree [v2,13/90] target/sparc: Move BPr to decodetree [v2,14/90] target/sparc: Move FBPfcc and FBfcc to decodetree [v2,15/90] target/sparc: Merge gen_cond with only caller [v2,16/90] target/sparc: Merge gen_fcond with only caller [v2,17/90] target/sparc: Merge gen_branch_[an] with only caller [v2,18/90] target/sparc: Pass DisasCompare to advance_jump_cond [v2,19/90] target/sparc: Move SETHI to decodetree [v2,20/90] target/sparc: Move Tcc to decodetree [v2,21/90] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree [v2,22/90] target/sparc: Move RDPSR, RDHPR to decodetree [v2,23/90] target/sparc: Move RDWIM, RDPR to decodetree [v2,24/90] target/sparc: Move RDTBR, FLUSHW to decodetree [v2,25/90] target/sparc: Move WRASR to decodetree [v2,26/90] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree [v2,27/90] target/sparc: Move WRWIM, WRPR to decodetree [v2,28/90] target/sparc: Move WRTBR, WRHPR to decodetree [v2,29/90] target/sparc: Move basic arithmetic to decodetree [v2,30/90] target/sparc: Move ADDC to decodetree [v2,31/90] target/sparc: Move MULX to decodetree [v2,32/90] target/sparc: Move UMUL, SMUL to decodetree [v2,33/90] target/sparc: Move SUBC to decodetree [v2,34/90] target/sparc: Move UDIVX, SDIVX to decodetree [v2,35/90] target/sparc: Move UDIV, SDIV to decodetree [v2,36/90] target/sparc: Move TADD, TSUB, MULS to decodetree [v2,37/90] target/sparc: Move SLL, SRL, SRA to decodetree [v2,38/90] target/sparc: Move MOVcc, MOVR to decodetree [v2,39/90] target/sparc: Move POPC to decodetree [v2,40/90] target/sparc: Convert remaining v8 coproc insns to decodetree [v2,41/90] target/sparc: Move JMPL, RETT, RETURN to decodetree [v2,42/90] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree [v2,43/90] target/sparc: Move DONE, RETRY to decodetree [v2,44/90] target/sparc: Split out resolve_asi [v2,45/90] target/sparc: Drop ifdef around get_asi and friends [v2,46/90] target/sparc: Split out ldst functions with asi pre-computed [v2,47/90] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX [v2,48/90] target/sparc: Move simple integer load/store to decodetree [v2,49/90] target/sparc: Move asi integer load/store to decodetree [v2,50/90] target/sparc: Move LDSTUB, LDSTUBA to decodetree [v2,51/90] target/sparc: Move SWAP, SWAPA to decodetree [v2,52/90] target/sparc: Move CASA, CASXA to decodetree [v2,53/90] target/sparc: Move PREFETCH, PREFETCHA to decodetree [v2,54/90] target/sparc: Split out fp ldst functions with asi precomputed [v2,55/90] target/sparc: Move simple fp load/store to decodetree [v2,56/90] target/sparc: Move asi fp load/store to decodetree [v2,57/90] target/sparc: Move LDFSR, STFSR to decodetree [v2,58/90] target/sparc: Merge LDFSR, LDXFSR implementations [v2,59/90] target/sparc: Move EDGE* to decodetree [v2,60/90] target/sparc: Move ARRAY* to decodetree [v2,61/90] target/sparc: Move ADDRALIGN* to decodetree [v2,62/90] target/sparc: Move BMASK to decodetree [v2,63/90] target/sparc: Move FMOVS, FNEGS, FABSS, FSRCS, FNOTS to decodetree [v2,64/90] target/sparc: Move FMOVD, FNEGD, FABSD, FSRCD, FNOTD to decodetree [v2,65/90] target/sparc: Use tcg_gen_vec_{add,sub}* [v2,66/90] target/sparc: Move gen_ne_fop_FFF insns to decodetree [v2,67/90] target/sparc: Move gen_ne_fop_DDD insns to decodetree [v2,68/90] target/sparc: Move PDIST to decodetree [v2,69/90] target/sparc: Move gen_gsr_fop_DDD insns to decodetree [v2,70/90] target/sparc: Move gen_fop_FF insns to decodetree [v2,71/90] target/sparc: Move gen_fop_DD insns to decodetree [v2,72/90] target/sparc: Move FSQRTq to decodetree [v2,73/90] target/sparc: Move gen_fop_FFF insns to decodetree [v2,74/90] target/sparc: Move gen_fop_DDD insns to decodetree [v2,75/90] target/sparc: Move gen_fop_QQQ insns to decodetree [v2,76/90] target/sparc: Move FSMULD to decodetree [v2,77/90] target/sparc: Move FDMULQ to decodetree [v2,78/90] target/sparc: Move gen_fop_FD insns to decodetree [v2,79/90] target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree [v2,80/90] target/sparc: Move FqTOs, FqTOi to decodetree [v2,81/90] target/sparc: Move FqTOd, FqTOx to decodetree [v2,82/90] target/sparc: Move FiTOq, FsTOq to decodetree [v2,83/90] target/sparc: Move FdTOq, FxTOq to decodetree [v2,84/90] target/sparc: Move FMOVq, FNEGq, FABSq to decodetree [v2,85/90] target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree [v2,86/90] target/sparc: Convert FCMP, FCMPE to decodetree [v2,87/90] target/sparc: Move FPCMP* to decodetree [v2,88/90] target/sparc: Move FPACK16, FPACKFIX to decodetree [v2,89/90] target/sparc: Convert FZERO, FONE to decodetree [v2,90/90] target/sparc: Remove disas_sparc_legacy

Message ID

20231017061244.681584-1-richard.henderson@linaro.org

Headers

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Subject: [PATCH v2 00/90] target/sparc: Convert to decodetree
Date: Mon, 16 Oct 2023 23:11:14 -0700
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Series

target/sparc: Convert to decodetree | expand

Message

Richard Henderson Oct. 17, 2023, 6:11 a.m. UTC

While doing some other testing the other day, I noticed my sparc64
chroot running particularly slowly.  I think I know what the problem
is there, but fixing that was going to be particularly ugly with the
existing sparc translator.

So I've converted the translator to something more managable.  :-)

Changes for v2:
  * Fixes for JMPL, RETT, SAVE and RESTORE.
  * Fixes for FMOV etc, which had lost gen_op_clear_ieee_excp_and_FTT.
  * Allow conditional exceptions to be raised out of line
    Use this for gen_check_align and conditional trap.
  * Keep properties and feature bits in sync.

r~

Richard Henderson (90):
  target/sparc: Clear may_lookup for npc == DYNAMIC_PC
  target/sparc: Implement check_align inline
  target/sparc: Avoid helper_raise_exception in helper_st_asi
  target/sparc: Set TCG_GUEST_DEFAULT_MO
  configs: Enable MTTCG for sparc, sparc64
  target/sparc: Define features via cpu-feature.h.inc
  target/sparc: Use CPU_FEATURE_BIT_* for cpu properties
  target/sparc: Remove sparcv7 cpu features
  target/sparc: Add decodetree infrastructure
  target/sparc: Define AM_CHECK for sparc32
  target/sparc: Move CALL to decodetree
  target/sparc: Move BPcc and Bicc to decodetree
  target/sparc: Move BPr to decodetree
  target/sparc: Move FBPfcc and FBfcc to decodetree
  target/sparc: Merge gen_cond with only caller
  target/sparc: Merge gen_fcond with only caller
  target/sparc: Merge gen_branch_[an] with only caller
  target/sparc: Pass DisasCompare to advance_jump_cond
  target/sparc: Move SETHI to decodetree
  target/sparc: Move Tcc to decodetree
  target/sparc: Move RDASR, STBAR, MEMBAR to decodetree
  target/sparc: Move RDPSR, RDHPR to decodetree
  target/sparc: Move RDWIM, RDPR to decodetree
  target/sparc: Move RDTBR, FLUSHW to decodetree
  target/sparc: Move WRASR to decodetree
  target/sparc: Move WRPSR, SAVED, RESTORED to decodetree
  target/sparc: Move WRWIM, WRPR to decodetree
  target/sparc: Move WRTBR, WRHPR to decodetree
  target/sparc: Move basic arithmetic to decodetree
  target/sparc: Move ADDC to decodetree
  target/sparc: Move MULX to decodetree
  target/sparc: Move UMUL, SMUL to decodetree
  target/sparc: Move SUBC to decodetree
  target/sparc: Move UDIVX, SDIVX to decodetree
  target/sparc: Move UDIV, SDIV to decodetree
  target/sparc: Move TADD, TSUB, MULS to decodetree
  target/sparc: Move SLL, SRL, SRA to decodetree
  target/sparc: Move MOVcc, MOVR to decodetree
  target/sparc: Move POPC to decodetree
  target/sparc: Convert remaining v8 coproc insns to decodetree
  target/sparc: Move JMPL, RETT, RETURN to decodetree
  target/sparc: Move FLUSH, SAVE, RESTORE to decodetree
  target/sparc: Move DONE, RETRY to decodetree
  target/sparc: Split out resolve_asi
  target/sparc: Drop ifdef around get_asi and friends
  target/sparc: Split out ldst functions with asi pre-computed
  target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for GET_ASI_DTWINX
  target/sparc: Move simple integer load/store to decodetree
  target/sparc: Move asi integer load/store to decodetree
  target/sparc: Move LDSTUB, LDSTUBA to decodetree
  target/sparc: Move SWAP, SWAPA to decodetree
  target/sparc: Move CASA, CASXA to decodetree
  target/sparc: Move PREFETCH, PREFETCHA to decodetree
  target/sparc: Split out fp ldst functions with asi precomputed
  target/sparc: Move simple fp load/store to decodetree
  target/sparc: Move asi fp load/store to decodetree
  target/sparc: Move LDFSR, STFSR to decodetree
  target/sparc: Merge LDFSR, LDXFSR implementations
  target/sparc: Move EDGE* to decodetree
  target/sparc: Move ARRAY* to decodetree
  target/sparc: Move ADDRALIGN* to decodetree
  target/sparc: Move BMASK to decodetree
  target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree
  target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree
  target/sparc: Use tcg_gen_vec_{add,sub}*
  target/sparc: Move gen_ne_fop_FFF insns to decodetree
  target/sparc: Move gen_ne_fop_DDD insns to decodetree
  target/sparc: Move PDIST to decodetree
  target/sparc: Move gen_gsr_fop_DDD insns to decodetree
  target/sparc: Move gen_fop_FF insns to decodetree
  target/sparc: Move gen_fop_DD insns to decodetree
  target/sparc: Move FSQRTq to decodetree
  target/sparc: Move gen_fop_FFF insns to decodetree
  target/sparc: Move gen_fop_DDD insns to decodetree
  target/sparc: Move gen_fop_QQQ insns to decodetree
  target/sparc: Move FSMULD to decodetree
  target/sparc: Move FDMULQ to decodetree
  target/sparc: Move gen_fop_FD insns to decodetree
  target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree
  target/sparc: Move FqTOs, FqTOi to decodetree
  target/sparc: Move FqTOd, FqTOx to decodetree
  target/sparc: Move FiTOq, FsTOq to decodetree
  target/sparc: Move FdTOq, FxTOq to decodetree
  target/sparc: Move FMOVq, FNEGq, FABSq to decodetree
  target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree
  target/sparc: Convert FCMP, FCMPE to decodetree
  target/sparc: Move FPCMP* to decodetree
  target/sparc: Move FPACK16, FPACKFIX to decodetree
  target/sparc: Convert FZERO, FONE to decodetree
  target/sparc: Remove disas_sparc_legacy

 configs/targets/sparc-softmmu.mak   |    1 +
 configs/targets/sparc64-softmmu.mak |    1 +
 linux-user/sparc/target_syscall.h   |    6 +-
 target/sparc/cpu.h                  |   76 +-
 target/sparc/helper.h               |   16 +-
 target/sparc/cpu-feature.h.inc      |   14 +
 target/sparc/insns.decode           |  540 +++
 target/sparc/cpu.c                  |   41 +-
 target/sparc/fop_helper.c           |   17 +-
 target/sparc/ldst_helper.c          |   17 +-
 target/sparc/translate.c            | 6833 +++++++++++++--------------
 target/sparc/vis_helper.c           |   59 -
 target/sparc/meson.build            |    3 +
 13 files changed, 3985 insertions(+), 3639 deletions(-)
 create mode 100644 target/sparc/cpu-feature.h.inc
 create mode 100644 target/sparc/insns.decode

Comments

Mark Cave-Ayland Oct. 17, 2023, 9:17 p.m. UTC | #1

On 17/10/2023 07:11, Richard Henderson wrote:

> While doing some other testing the other day, I noticed my sparc64
> chroot running particularly slowly.  I think I know what the problem
> is there, but fixing that was going to be particularly ugly with the
> existing sparc translator.
> 
> So I've converted the translator to something more managable.  :-)
> 
> Changes for v2:
>    * Fixes for JMPL, RETT, SAVE and RESTORE.
>    * Fixes for FMOV etc, which had lost gen_op_clear_ieee_excp_and_FTT.
>    * Allow conditional exceptions to be raised out of line
>      Use this for gen_check_align and conditional trap.
>    * Keep properties and feature bits in sync.
> 
> r~
> 
> Richard Henderson (90):
>    target/sparc: Clear may_lookup for npc == DYNAMIC_PC
>    target/sparc: Implement check_align inline
>    target/sparc: Avoid helper_raise_exception in helper_st_asi
>    target/sparc: Set TCG_GUEST_DEFAULT_MO
>    configs: Enable MTTCG for sparc, sparc64
>    target/sparc: Define features via cpu-feature.h.inc
>    target/sparc: Use CPU_FEATURE_BIT_* for cpu properties
>    target/sparc: Remove sparcv7 cpu features
>    target/sparc: Add decodetree infrastructure
>    target/sparc: Define AM_CHECK for sparc32
>    target/sparc: Move CALL to decodetree
>    target/sparc: Move BPcc and Bicc to decodetree
>    target/sparc: Move BPr to decodetree
>    target/sparc: Move FBPfcc and FBfcc to decodetree
>    target/sparc: Merge gen_cond with only caller
>    target/sparc: Merge gen_fcond with only caller
>    target/sparc: Merge gen_branch_[an] with only caller
>    target/sparc: Pass DisasCompare to advance_jump_cond
>    target/sparc: Move SETHI to decodetree
>    target/sparc: Move Tcc to decodetree
>    target/sparc: Move RDASR, STBAR, MEMBAR to decodetree
>    target/sparc: Move RDPSR, RDHPR to decodetree
>    target/sparc: Move RDWIM, RDPR to decodetree
>    target/sparc: Move RDTBR, FLUSHW to decodetree
>    target/sparc: Move WRASR to decodetree
>    target/sparc: Move WRPSR, SAVED, RESTORED to decodetree
>    target/sparc: Move WRWIM, WRPR to decodetree
>    target/sparc: Move WRTBR, WRHPR to decodetree
>    target/sparc: Move basic arithmetic to decodetree
>    target/sparc: Move ADDC to decodetree
>    target/sparc: Move MULX to decodetree
>    target/sparc: Move UMUL, SMUL to decodetree
>    target/sparc: Move SUBC to decodetree
>    target/sparc: Move UDIVX, SDIVX to decodetree
>    target/sparc: Move UDIV, SDIV to decodetree
>    target/sparc: Move TADD, TSUB, MULS to decodetree
>    target/sparc: Move SLL, SRL, SRA to decodetree
>    target/sparc: Move MOVcc, MOVR to decodetree
>    target/sparc: Move POPC to decodetree
>    target/sparc: Convert remaining v8 coproc insns to decodetree
>    target/sparc: Move JMPL, RETT, RETURN to decodetree
>    target/sparc: Move FLUSH, SAVE, RESTORE to decodetree
>    target/sparc: Move DONE, RETRY to decodetree
>    target/sparc: Split out resolve_asi
>    target/sparc: Drop ifdef around get_asi and friends
>    target/sparc: Split out ldst functions with asi pre-computed
>    target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for GET_ASI_DTWINX
>    target/sparc: Move simple integer load/store to decodetree
>    target/sparc: Move asi integer load/store to decodetree
>    target/sparc: Move LDSTUB, LDSTUBA to decodetree
>    target/sparc: Move SWAP, SWAPA to decodetree
>    target/sparc: Move CASA, CASXA to decodetree
>    target/sparc: Move PREFETCH, PREFETCHA to decodetree
>    target/sparc: Split out fp ldst functions with asi precomputed
>    target/sparc: Move simple fp load/store to decodetree
>    target/sparc: Move asi fp load/store to decodetree
>    target/sparc: Move LDFSR, STFSR to decodetree
>    target/sparc: Merge LDFSR, LDXFSR implementations
>    target/sparc: Move EDGE* to decodetree
>    target/sparc: Move ARRAY* to decodetree
>    target/sparc: Move ADDRALIGN* to decodetree
>    target/sparc: Move BMASK to decodetree
>    target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree
>    target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree
>    target/sparc: Use tcg_gen_vec_{add,sub}*
>    target/sparc: Move gen_ne_fop_FFF insns to decodetree
>    target/sparc: Move gen_ne_fop_DDD insns to decodetree
>    target/sparc: Move PDIST to decodetree
>    target/sparc: Move gen_gsr_fop_DDD insns to decodetree
>    target/sparc: Move gen_fop_FF insns to decodetree
>    target/sparc: Move gen_fop_DD insns to decodetree
>    target/sparc: Move FSQRTq to decodetree
>    target/sparc: Move gen_fop_FFF insns to decodetree
>    target/sparc: Move gen_fop_DDD insns to decodetree
>    target/sparc: Move gen_fop_QQQ insns to decodetree
>    target/sparc: Move FSMULD to decodetree
>    target/sparc: Move FDMULQ to decodetree
>    target/sparc: Move gen_fop_FD insns to decodetree
>    target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree
>    target/sparc: Move FqTOs, FqTOi to decodetree
>    target/sparc: Move FqTOd, FqTOx to decodetree
>    target/sparc: Move FiTOq, FsTOq to decodetree
>    target/sparc: Move FdTOq, FxTOq to decodetree
>    target/sparc: Move FMOVq, FNEGq, FABSq to decodetree
>    target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree
>    target/sparc: Convert FCMP, FCMPE to decodetree
>    target/sparc: Move FPCMP* to decodetree
>    target/sparc: Move FPACK16, FPACKFIX to decodetree
>    target/sparc: Convert FZERO, FONE to decodetree
>    target/sparc: Remove disas_sparc_legacy
> 
>   configs/targets/sparc-softmmu.mak   |    1 +
>   configs/targets/sparc64-softmmu.mak |    1 +
>   linux-user/sparc/target_syscall.h   |    6 +-
>   target/sparc/cpu.h                  |   76 +-
>   target/sparc/helper.h               |   16 +-
>   target/sparc/cpu-feature.h.inc      |   14 +
>   target/sparc/insns.decode           |  540 +++
>   target/sparc/cpu.c                  |   41 +-
>   target/sparc/fop_helper.c           |   17 +-
>   target/sparc/ldst_helper.c          |   17 +-
>   target/sparc/translate.c            | 6833 +++++++++++++--------------
>   target/sparc/vis_helper.c           |   59 -
>   target/sparc/meson.build            |    3 +
>   13 files changed, 3985 insertions(+), 3639 deletions(-)
>   create mode 100644 target/sparc/cpu-feature.h.inc
>   create mode 100644 target/sparc/insns.decode

Thanks again for working on this :)  I've done a re-run of my 32-bit SPARC tests and 
things are looking fairly good now, although there were still a small number of failures:

[1] ./qemu-system-sparc -bios ss5.bin

-> Now traps immediately on startup
qemu: fatal: Trap 0x02 (Illegal Instruction) while interrupts disabled, Error state
pc: ffeff020  npc: ffeff024
%g0-7: 00000000 ffffffff ffd15a00 ffef0000 00000002 ffd17384 ffefefd8 ffefebd0
%o0-7: 7000cbcf 0007ffff 00080000 00000000 0000001e 07fee5fc 00000000 0000caf0
%l0-7: 07fff000 ffd173f0 ffd173f4 07fef000 07feec00 00000000 00000000 00000000
%i0-7: 01fee000 00001000 00000000 00000000 00000000 0000beec 0002aa2c ffd1e080
%f00:  0000000000000000 0000000000000000 0000000000000000 0000000000000000
%f08:  0000000000000000 0000000000000000 0000000000000000 0000000000000000
%f16:  0000000000000000 0000000000000000 0000000000000000 0000000000000000
%f24:  0000000000000000 0000000000000000 0000000000000000 0000000000000000
psr: 04000fc7 (icc: ---- SPE: SP-) wim: 00000000
fsr: 00000000 y: 00000000

Aborted (core dumped)

-> Bisected to:

6c8bf6bbe369c7cda82aaba63a19508e8cff5085 is the first bad commit
commit 6c8bf6bbe369c7cda82aaba63a19508e8cff5085
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Mon Oct 16 23:11:34 2023 -0700

     target/sparc: Move Tcc to decodetree

     Use the new delay_exceptionv function in the implementation.

     Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
     Message-Id: <20231017061244.681584-21-richard.henderson@linaro.org>

  target/sparc/insns.decode |   2 +
  target/sparc/translate.c  | 143 +++++++++++++++++++++-------------------------
  2 files changed, 66 insertions(+), 79 deletions(-)


[2] ./qemu-system-sparc -hda net702.qcow -snapshot   (NetBSD 7)

-> Hangs after displaying "Starting network"

-> Bisected to:

db639ccbdce25dde5e767f3da1ff40e29067610c is the first bad commit
commit db639ccbdce25dde5e767f3da1ff40e29067610c
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Mon Oct 16 23:11:44 2023 -0700

     target/sparc: Move ADDC to decodetree

     Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
     Message-Id: <20231017061244.681584-31-richard.henderson@linaro.org>

  target/sparc/insns.decode |  2 ++
  target/sparc/translate.c  | 41 +++++++++++++++++++++++++++++++++++++----
  2 files changed, 39 insertions(+), 4 deletions(-)


[3] ./qemu-system-sparc -cdrom NetBSD-6.1.3-sparc.iso -boot d

-> Displays "write failed, filesystem full" and "Segmentation Fault" error messages 
during boot

-> Bisected to:

db639ccbdce25dde5e767f3da1ff40e29067610c is the first bad commit
commit db639ccbdce25dde5e767f3da1ff40e29067610c
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Mon Oct 16 23:11:44 2023 -0700

     target/sparc: Move ADDC to decodetree

     Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
     Message-Id: <20231017061244.681584-31-richard.henderson@linaro.org>

  target/sparc/insns.decode |  2 ++
  target/sparc/translate.c  | 41 +++++++++++++++++++++++++++++++++++++----
  2 files changed, 39 insertions(+), 4 deletions(-)



ATB,

Mark.