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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id h24-20020a170902ac9800b001c3be750900sm4164324plr.163.2023.10.13.10.51.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 10:51:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 0/2] tcg: Streamline vector load/store Date: Fri, 13 Oct 2023 10:51:07 -0700 Message-Id: <20231013175109.124308-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We have tcg_gen_qemu_{ld,st}_i128, which can be used to implement load/store of vectors to guest memory. But at present we have to split into, or concatenated from, two i64 to reference the guest vector register backing store within env. Provide tcg_gen_{ld,st}_i128, which can avoid the trip through i64. This does require that the target store i128 in host byte ordering, which is true of i386 (and some other backends) but not arm or s390x. There is definitely further cleanup possible. Changes for v2: * Set atomicity for x86 vector operations. r~ Richard Henderson (2): tcg: Add tcg_gen_{ld,st}_i128 target/i386: Use i128 for 128 and 256-bit loads and stores include/tcg/tcg-op-common.h | 3 ++ target/i386/tcg/translate.c | 63 +++++++++++++++++-------------------- tcg/tcg-op.c | 22 +++++++++++++ 3 files changed, 54 insertions(+), 34 deletions(-)