From patchwork Tue Oct 10 09:28:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731431 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1640440wrw; Tue, 10 Oct 2023 02:30:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGIroVS+adARpamMWSG7HH9yNw829P+l184nMGQ+qMFra+Hbc8J3Hwrmib3P3bDqu8sti6D X-Received: by 2002:a05:620a:13d3:b0:773:af88:ccf2 with SMTP id g19-20020a05620a13d300b00773af88ccf2mr17416468qkl.56.1696930222116; Tue, 10 Oct 2023 02:30:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930222; cv=none; d=google.com; s=arc-20160816; b=wqbKqSm9IJvo8ETc1xaHb+OAVBL4pfU8HGw8y3vgNU6nasZy11ZfsMHbVptCzLYXJ/ 0vMyD549s0+pFecL52j4NrRal4l2Bq1Q7wAz3HFAC+t/C0nF0N+rHfHWM/ycDTNFYr7b yqmIq4GQLFDUC4kOda/RxFcbFhNNpkgt4232BHMBuOFFaavlm09rCPeBxyFKarJOj26K fA4JAHpD55ENyNioWhuoDetS4EQHblJMTVKCZT+HVv8I/8lKSAw7y2tTtJ31b6qMefKP VRxETRlWxdQH5AVZI5w7darhJZeFLQmcGJ+PqY6UU5XYFIk9gziajFNV7NXdj6zRIHbj pGkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature; bh=jVdFJHte50YKA8Z2cBZMBa58ygStm0gO7g9CZPgou1U=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=HSIXMj0hz1JL4+y9GwEWpBSVOJ+NpLnT9oU+iOkGY4e7aLk51k5zlXvtwKPS4EQTXN /GW2rYuj/5T/IwHoa3qLMVQMgq5uQpoR22QkfNA1CU/X8YQ/B5pr5/bdoA9JUHOdAmEh f9qeaOFhJPUfX+rVqJcUcE3/fkESNddMM6XrTlTmQq0Ot0Ncn3y2dHaC50oy0HH7IWl+ CM3Dl5OrqZcMQsoyRMjufvu47i4+Gx+uNONaxQ9q7B87mUUqXiXIBHuUfFYL3vVZbjZl aeITTCdblvSNhcD54DwbTZy2aaabKvfku60oq1M6G2h/VGmeV+Y5Kq1rqoERaN6xKaI0 Wf5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mpnjiPEr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id dv13-20020a05620a1b8d00b0076ef653ac9fsi7403265qkb.127.2023.10.10.02.30.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2023 02:30:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mpnjiPEr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qq93B-0007qR-DU; Tue, 10 Oct 2023 05:29:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qq939-0007p4-Ke for qemu-devel@nongnu.org; Tue, 10 Oct 2023 05:29:11 -0400 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qq936-0007d2-JZ for qemu-devel@nongnu.org; Tue, 10 Oct 2023 05:29:11 -0400 Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-9ba1eb73c27so335019466b.3 for ; Tue, 10 Oct 2023 02:29:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696930147; x=1697534947; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=jVdFJHte50YKA8Z2cBZMBa58ygStm0gO7g9CZPgou1U=; b=mpnjiPErYC89McTVpbwqkKsP+cn8mDk/QMWg9N2LytlpKfNuXLvO2bI+PbwpqkjRIm 8vxTFXHviucT++bhe2X2MWIvVHluIRp0l/t6Nn6nqedZp6iumKJ9XiUULdFFxnTiG8zl 8jS2GSdBJntH3GaoArxUziVX4tqUjoixKp+3Ix9r/W37UTQIG9AiNVaZ2YHcOJz4Oqda sr85tAWimYhl4AMNmGNQlxQrG3VZ3D3qnz9JGXgaKx1z8QPYS6shmFuYIduetpvtn1wT jjfAgoNotecCd0z0pWsyXjrtiHjbL5Eo+kKQpU4o6FWKY7lEE5J39n9WcDToVkCZ/UR+ K89A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696930147; x=1697534947; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=jVdFJHte50YKA8Z2cBZMBa58ygStm0gO7g9CZPgou1U=; b=d1o6NaUpwrEfj5GEN+3RGlXVBrRsWKdfKCsNN+pliEXrfUFjHDmdZliiMbn1Z3TeEs OQ8mFym9MhynU2MqfVGMsoiphMe86vMnZrb4CjIdZ1WYEghcH0GeFmM+/rmaxrFDGdGG gD1lforygc9mNG3PF0kGAMKcywzpSk9fKAKKu834wD6hvto00VQGUpjqNZs0q8Nf/VFO y/h/fGYU0y3ljkj62eKEAoGOsxjwQSb9mTaXX1y1QBgV+FatphY7U0yCafrOuUlYVmX3 AANavgL4Ic8Hu2KbrcoutZFphSPugK2ifHWdhSENLdLXiClop1SOZLlsKlGCxkWmbgy8 46yg== X-Gm-Message-State: AOJu0YzFxaW3keCPfEt0q9tE/QJdAU8+rdcBcjxN1WB9x7mLKMLjHDlA lDToH9YUpO2MZmYPAskcmUTCuNWEdrmB1O4spfka4Q== X-Received: by 2002:a17:906:2250:b0:9ae:54ea:5b0f with SMTP id 16-20020a170906225000b009ae54ea5b0fmr17025641ejr.24.1696930146660; Tue, 10 Oct 2023 02:29:06 -0700 (PDT) Received: from m1x-phil.lan (aif79-h01-176-172-113-148.dsl.sta.abo.bbox.fr. [176.172.113.148]) by smtp.gmail.com with ESMTPSA id f23-20020a170906139700b009a5f1d15642sm8105155ejc.158.2023.10.10.02.29.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:29:06 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 00/18] target: Make 'cpu-qom.h' really target agnostic Date: Tue, 10 Oct 2023 11:28:42 +0200 Message-ID: <20231010092901.99189-1-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org A heterogeneous machine must be able to instantiate CPUs from different architectures. In order to do that, the common hw/ code has to access to the QOM CPU definitions from various architecture. Those QOM definitions are published in "target/foo/cpu-qom.h". All 'cpu-qom.h' must be target agnostic, so hw/ can include multiple of them in order to create a heterogeneous machine. This series strengthen all (except PPC...) target 'cpu-qom.h', making them target agnostic. For various targets it is just a matter of moving definitions where they belong (either 'cpu.h' or 'cpu-qom.h'). For few (mips/riscv/sparc/x86) we have to remove the target specific definitions (which 'taint' the header as target specific). For mips/sparc/x86 this implies splitting the base target definition by making it explicit to the build type (32 or 64-bit). PPC is missing because CPU types are currently registered indistinctly, and whether a CPU is 32/64 bit can not be detected at build time (it is done in each cpu_class_init() handler, *after* the type is registered). Based-on: <20231010074952.79165-1-philmd@linaro.org> Introduce qtest_get_base_arch() / qtest_get_arch_bits() Philippe Mathieu-Daudé (18): target: Mention 'cpu-qom.h' is target agnostic target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h' target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h' target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' target/hexagon: Declare QOM definitions in 'cpu-qom.h' target/loongarch: Declare QOM definitions in 'cpu-qom.h' target/nios2: Declare QOM definitions in 'cpu-qom.h' target/openrisc: Declare QOM definitions in 'cpu-qom.h' target/i386: Inline target specific TARGET_DEFAULT_CPU_TYPE definition target/riscv: Inline target specific TYPE_RISCV_CPU_BASE definition target/i386: Declare CPU QOM types using DEFINE_TYPES() macro target/mips: Declare CPU QOM types using DEFINE_TYPES() macro target/ppc: Declare CPU QOM types using DEFINE_TYPES() macro target/sparc: Declare CPU QOM types using DEFINE_TYPES() macro cpus: Open code OBJECT_DECLARE_TYPE() in OBJECT_DECLARE_CPU_TYPE() target/i386: Make X86_CPU common to new I386_CPU / X86_64_CPU types target/mips: Make MIPS_CPU common to new MIPS32_CPU / MIPS64_CPU types target/sparc: Make SPARC_CPU common to new SPARC32_CPU/SPARC64_CPU types include/hw/core/cpu.h | 7 +++- target/alpha/cpu-qom.h | 5 ++- target/alpha/cpu.h | 2 -- target/arm/cpu-qom.h | 2 +- target/avr/cpu-qom.h | 5 ++- target/avr/cpu.h | 2 -- target/cris/cpu-qom.h | 5 ++- target/cris/cpu.h | 2 -- target/hexagon/cpu-qom.h | 35 ++++++++++++++++++++ target/hexagon/cpu.h | 23 +------------ target/hppa/cpu-qom.h | 2 +- target/i386/cpu-qom.h | 19 +++++++---- target/i386/cpu.h | 11 ++----- target/loongarch/cpu-qom.h | 38 +++++++++++++++++++++ target/loongarch/cpu.h | 26 +-------------- target/m68k/cpu-qom.h | 5 ++- target/m68k/cpu.h | 2 -- target/microblaze/cpu-qom.h | 2 +- target/mips/cpu-qom.h | 16 +++++---- target/mips/cpu.h | 5 +-- target/nios2/cpu-qom.h | 32 ++++++++++++++++++ target/nios2/cpu.h | 22 +------------ target/openrisc/cpu-qom.h | 36 ++++++++++++++++++++ target/openrisc/cpu.h | 26 +-------------- target/ppc/cpu-qom.h | 3 +- target/ppc/cpu.h | 2 ++ target/riscv/cpu-qom.h | 9 +---- target/riscv/cpu.h | 2 ++ target/rx/cpu-qom.h | 5 ++- target/rx/cpu.h | 2 -- target/s390x/cpu-qom.h | 5 ++- target/s390x/cpu.h | 2 -- target/sh4/cpu-qom.h | 5 ++- target/sh4/cpu.h | 2 -- target/sparc/cpu-qom.h | 14 ++++---- target/sparc/cpu.h | 5 +-- target/tricore/cpu-qom.h | 5 +++ target/tricore/cpu.h | 2 -- target/xtensa/cpu-qom.h | 5 ++- target/xtensa/cpu.h | 2 -- hw/i386/microvm.c | 6 +++- hw/i386/pc.c | 6 +++- hw/riscv/spike.c | 8 ++++- hw/riscv/virt.c | 8 ++++- target/i386/cpu.c | 66 ++++++++++++++++++++++--------------- target/mips/cpu.c | 34 ++++++++++++------- target/ppc/cpu_init.c | 52 +++++++++++++---------------- target/sparc/cpu.c | 35 +++++++++++++------- tests/qtest/cpu-plug-test.c | 2 +- 49 files changed, 369 insertions(+), 248 deletions(-) create mode 100644 target/hexagon/cpu-qom.h create mode 100644 target/loongarch/cpu-qom.h create mode 100644 target/nios2/cpu-qom.h create mode 100644 target/openrisc/cpu-qom.h