Message ID | 20230915185453.1871167-1-peter.maydell@linaro.org |
---|---|
Headers | show |
Series | target/arm: Implement Neoverse-N2 | expand |
W dniu 15.09.2023 o 20:54, Peter Maydell pisze: > This patchset implements a model of the Neoverse-N2 CPU. > Because it's very similar to the Cortex-A710 we don't > need to implement any new features for it; but because it > supports 48 bit physical addresses we can use it in the > sbsa-ref board. > > Patch 1 fixes a few minor errors in the A710 definition > that I spotted while I was cross-checking it against the > N2 TRM to see what had changed. > > Patch 2 is the new CPU model. Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> root@sbsa-ref:~# lscpu Architecture: aarch64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 2 On-line CPU(s) list: 0,1 Vendor ID: ARM BIOS Vendor ID: QEMU Model name: Neoverse-N2
Ping for code review -- Richard or Alex, maybe ? thanks -- PMM On Fri, 15 Sept 2023 at 19:54, Peter Maydell <peter.maydell@linaro.org> wrote: > > This patchset implements a model of the Neoverse-N2 CPU. > Because it's very similar to the Cortex-A710 we don't > need to implement any new features for it; but because it > supports 48 bit physical addresses we can use it in the > sbsa-ref board. > > Patch 1 fixes a few minor errors in the A710 definition > that I spotted while I was cross-checking it against the > N2 TRM to see what had changed. > > Patch 2 is the new CPU model. > > thanks > -- PMM > > Peter Maydell (2): > target/arm: Correct minor errors in Cortex-A710 definition > target/arm: Implement Neoverse N2 CPU model > > docs/system/arm/virt.rst | 1 + > hw/arm/sbsa-ref.c | 1 + > hw/arm/virt.c | 1 + > target/arm/tcg/cpu64.c | 114 ++++++++++++++++++++++++++++++++++++++- > 4 files changed, 115 insertions(+), 2 deletions(-)