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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r3-20020a5d4983000000b00317ab75748bsm10079758wrq.49.2023.09.11.06.53.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 06:53:42 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/7] target/arm: hwcaps updates, FEAT_HBC Date: Mon, 11 Sep 2023 14:53:33 +0100 Message-Id: <20230911135340.1139553-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This patchset started off as "implement FEAT_HBC" but I ended up finding I needed to do a bit of cleanup regarding the elf hwcaps bits, so most of the patchset is that cleanup and the FEAT_HBC is the simple patch at the end. Patch 1 is the ID_AA64ISAR2_EL1 that's been on the list multiple times already. It's in a target-arm pullreq that's already on the list, so I've only included it here so the series compiles as a standalone patchset. Patch 2 is a bugfix for some errors in feature string names in the emulated /proc/cpuinfo. Patches 3-6 update our definitions of hwcap bit values from the current Linux kernel source tree, our ID register field definitions from the current public system register XML, and make sure we're in sync with the kernel about what hwcap bits we report and what ID register fields we expose to user-only guest processes. (The only actual bug fixed here is some missing arm32 hwcap bits, but the rest of the changes are useful to, for instance, let us add FEAT_HBC support.) Patch 7 is the actual FEAT_HBC support. This feature is a variant on the B.cond conditional branch that provides some hint information to the branch predictor; since we don't do branch prediction this is easy for us to implement. Patch 7 will have an obvious trivial textual conflict with the FEAT_MOPS work; I suspect this will get in first, since it's much simpler. I also forgot about the hwcap for FEAT_MOPS, but once these patches are applied that is a one-liner fix to add the GET_FEATURE_ID(aa64_mops, ARM_HWCAP2_A64_MOPS). thanks -- PMM Aaron Lindsay (1): target/arm: Add ID_AA64ISAR2_EL1 Peter Maydell (6): linux-user/elfload.c: Correct SME feature names reported in cpuinfo linux-user/elfload.c: Add missing arm and arm64 hwcap values linux-user/elfload.c: Report previously missing arm32 hwcaps target/arm: Update AArch64 ID register field definitions target/arm: Update user-mode ID reg mask values target/arm: Implement FEAT_HBC docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 28 ++++++++++++++ target/arm/tcg/a64.decode | 3 +- linux-user/elfload.c | 71 ++++++++++++++++++++++++++++++---- target/arm/helper.c | 15 +++++-- target/arm/hvf/hvf.c | 1 + target/arm/kvm64.c | 2 + target/arm/tcg/cpu64.c | 4 ++ target/arm/tcg/translate-a64.c | 4 ++ 9 files changed, 118 insertions(+), 11 deletions(-) Reviewed-by: Richard Henderson