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([2602:47:d483:7301:e773:351d:2db2:8a8a]) by smtp.gmail.com with ESMTPSA id gk18-20020a17090b119200b00263ba6a248bsm5723840pjb.1.2023.08.11.14.40.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Aug 2023 14:40:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 00/11] target/arm: Implement cortex-a710 Date: Fri, 11 Aug 2023 14:40:20 -0700 Message-Id: <20230811214031.171020-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is one of the first generation Armv9 cores, and gives us something concrete to test in that area. Notably, it supports MTE. Changes for v2: * Check GMBS during realize. * Fix access checks for neoverse implementation registers. Mostly just traps EL1/EL2 if EL2/EL3 enabled. * Add make_ccsidr64 helper. * Reduce MTE with no tag memory to MTE=1. * Suppress FEAT_TRBE. * Implement HPDS2 as a no-op. * Rewrite a710 implementation registers; do try to share code with neoverse, because the traps are different. This of course solves the renaming and renumbering issues too. r~ Richard Henderson (11): target/arm: Reduce dcz_blocksize to uint8_t target/arm: Allow cpu to configure GM blocksize target/arm: Support more GM blocksizes target/arm: When tag memory is not present, set MTE=1 target/arm: Introduce make_ccsidr64 target/arm: Apply access checks to neoverse-n1 special registers target/arm: Apply access checks to neoverse-v1 special registers target/arm: Implement RMR_EL3 for neoverse-v1 target/arm: Suppress FEAT_TRBE (Trace Buffer Extension) target/arm: Implement FEAT_HPDS2 as a no-op target/arm: Implement cortex-a710 docs/system/arm/emulation.rst | 1 + docs/system/arm/virt.rst | 1 + target/arm/cpregs.h | 2 + target/arm/cpu.h | 5 +- target/arm/internals.h | 6 - target/arm/tcg/translate.h | 2 + hw/arm/virt.c | 1 + target/arm/cpu.c | 28 ++- target/arm/helper.c | 15 +- target/arm/tcg/cpu32.c | 2 +- target/arm/tcg/cpu64.c | 347 ++++++++++++++++++++++++++++++--- target/arm/tcg/mte_helper.c | 90 +++++++-- target/arm/tcg/translate-a64.c | 5 +- 13 files changed, 437 insertions(+), 68 deletions(-)