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[188.79.232.91]) by smtp.gmail.com with ESMTPSA id t5-20020a05600001c500b00313f7b077fesm18446562wrx.59.2023.07.03.03.05.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jul 2023 03:05:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, alistair.francis@wdc.com, danielhb413@gmail.com Subject: [PATCH v4 00/37] crypto: Provide aes-round.h and host accel Date: Mon, 3 Jul 2023 12:04:43 +0200 Message-Id: <20230703100520.68224-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Inspired by Ard Biesheuvel's RFC patches for accelerating AES under emulation, provide a set of primitives that maps between the guest and host fragments. Changes for v4: * Fix typo in AESState (Max Chou) * Define AES_SH/ISH as macros (Ard Biesheuvel) * Group patches by subsystem. Patches lacking review: 12-host-include-i386-Implement-aes-round.h.patch 13-host-include-aarch64-Implement-aes-round.h.patch 21-target-i386-Use-aesdec_IMC.patch 22-target-i386-Use-aesenc_SB_SR_MC_AK.patch 23-target-i386-Use-aesdec_ISB_ISR_IMC_AK.patch 25-target-arm-Use-aesenc_SB_SR_AK.patch 26-target-arm-Use-aesdec_ISB_ISR_AK.patch 27-target-arm-Use-aesenc_MC.patch 28-target-arm-Use-aesdec_IMC.patch 29-target-riscv-Use-aesenc_SB_SR_AK.patch 30-target-riscv-Use-aesdec_ISB_ISR_AK.patch 31-target-riscv-Use-aesdec_IMC.patch 32-target-riscv-Use-aesenc_SB_SR_MC_AK.patch 33-target-riscv-Use-aesdec_ISB_ISR_IMC_AK.patch Daniel(s), I could push the set that has been reviewed (crypto/, DPB; target/ppc/, DHB) through tcg-next if you like, just to reduce the outstanding set. Perhaps smaller patch sets would help getting the other targets reviewed... r~ Richard Henderson (37): util: Add cpuinfo-ppc.c tests/multiarch: Add test-aes target/arm: Move aesmc and aesimc tables to crypto/aes.c crypto/aes: Add AES_SH, AES_ISH macros crypto: Add aesenc_SB_SR_AK crypto: Add aesdec_ISB_ISR_AK crypto: Add aesenc_MC crypto: Add aesdec_IMC crypto: Add aesenc_SB_SR_MC_AK crypto: Add aesdec_ISB_ISR_IMC_AK crypto: Add aesdec_ISB_ISR_AK_IMC host/include/i386: Implement aes-round.h host/include/aarch64: Implement aes-round.h host/include/ppc: Implement aes-round.h target/ppc: Use aesenc_SB_SR_AK target/ppc: Use aesdec_ISB_ISR_AK target/ppc: Use aesenc_SB_SR_MC_AK target/ppc: Use aesdec_ISB_ISR_AK_IMC target/i386: Use aesenc_SB_SR_AK target/i386: Use aesdec_ISB_ISR_AK target/i386: Use aesdec_IMC target/i386: Use aesenc_SB_SR_MC_AK target/i386: Use aesdec_ISB_ISR_IMC_AK target/arm: Demultiplex AESE and AESMC target/arm: Use aesenc_SB_SR_AK target/arm: Use aesdec_ISB_ISR_AK target/arm: Use aesenc_MC target/arm: Use aesdec_IMC target/riscv: Use aesenc_SB_SR_AK target/riscv: Use aesdec_ISB_ISR_AK target/riscv: Use aesdec_IMC target/riscv: Use aesenc_SB_SR_MC_AK target/riscv: Use aesdec_ISB_ISR_IMC_AK crypto: Remove AES_shifts, AES_ishifts crypto: Implement aesdec_IMC with AES_imc_rot crypto: Remove AES_imc crypto: Unexport AES_*_rot, AES_TeN, AES_TdN MAINTAINERS | 1 + meson.build | 9 + host/include/aarch64/host/cpuinfo.h | 1 + host/include/aarch64/host/crypto/aes-round.h | 205 +++++ host/include/generic/host/crypto/aes-round.h | 33 + host/include/i386/host/cpuinfo.h | 1 + host/include/i386/host/crypto/aes-round.h | 152 ++++ host/include/ppc/host/cpuinfo.h | 30 + host/include/ppc/host/crypto/aes-round.h | 182 +++++ host/include/ppc64/host/cpuinfo.h | 1 + host/include/ppc64/host/crypto/aes-round.h | 1 + host/include/x86_64/host/crypto/aes-round.h | 1 + include/crypto/aes-round.h | 164 ++++ include/crypto/aes.h | 30 - target/arm/helper.h | 2 + target/i386/ops_sse.h | 60 +- tcg/ppc/tcg-target.h | 16 +- target/arm/tcg/sve.decode | 4 +- crypto/aes.c | 780 ++++++++++++------- target/arm/tcg/crypto_helper.c | 249 ++---- target/arm/tcg/translate-a64.c | 13 +- target/arm/tcg/translate-neon.c | 4 +- target/arm/tcg/translate-sve.c | 8 +- target/ppc/int_helper.c | 50 +- target/riscv/crypto_helper.c | 138 +--- tests/tcg/aarch64/test-aes.c | 58 ++ tests/tcg/i386/test-aes.c | 68 ++ tests/tcg/ppc64/test-aes.c | 116 +++ tests/tcg/riscv64/test-aes.c | 76 ++ util/cpuinfo-aarch64.c | 2 + util/cpuinfo-i386.c | 3 + util/cpuinfo-ppc.c | 64 ++ tcg/ppc/tcg-target.c.inc | 44 +- tests/tcg/multiarch/test-aes-main.c.inc | 183 +++++ tests/tcg/aarch64/Makefile.target | 4 + tests/tcg/i386/Makefile.target | 4 + tests/tcg/ppc64/Makefile.target | 1 + tests/tcg/riscv64/Makefile.target | 13 + util/meson.build | 2 + 39 files changed, 2049 insertions(+), 724 deletions(-) create mode 100644 host/include/aarch64/host/crypto/aes-round.h create mode 100644 host/include/generic/host/crypto/aes-round.h create mode 100644 host/include/i386/host/crypto/aes-round.h create mode 100644 host/include/ppc/host/cpuinfo.h create mode 100644 host/include/ppc/host/crypto/aes-round.h create mode 100644 host/include/ppc64/host/cpuinfo.h create mode 100644 host/include/ppc64/host/crypto/aes-round.h create mode 100644 host/include/x86_64/host/crypto/aes-round.h create mode 100644 include/crypto/aes-round.h create mode 100644 tests/tcg/aarch64/test-aes.c create mode 100644 tests/tcg/i386/test-aes.c create mode 100644 tests/tcg/ppc64/test-aes.c create mode 100644 tests/tcg/riscv64/test-aes.c create mode 100644 util/cpuinfo-ppc.c create mode 100644 tests/tcg/multiarch/test-aes-main.c.inc