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[209.51.188.17]) by mx.google.com with ESMTPS id n22-20020ac85b56000000b003f21c565b9asi1721159qtw.681.2023.06.26.16.23.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Jun 2023 16:23:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Na1hPYzB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qDvVV-0004aH-AM; Mon, 26 Jun 2023 19:20:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qDvVJ-0004Ys-NX for qemu-devel@nongnu.org; Mon, 26 Jun 2023 19:20:21 -0400 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qDvVH-0008Bm-26 for qemu-devel@nongnu.org; Mon, 26 Jun 2023 19:20:17 -0400 Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-98df3dea907so348893166b.3 for ; Mon, 26 Jun 2023 16:20:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687821611; x=1690413611; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Wv9Tq5llbl/sjP52djumXiDvzm3itZBu/GStUzP7o5Y=; b=Na1hPYzB8PgQSQ40PeilqNmyYUXY1NeW0ffvN9IpsQ89e1gH1bZoEDZwVM4iZmE0DV y8XPg9jQUfgQFWE+Su2SWViRR+HbLZJqx6UUg1BD5VUJG3xL58gIXqEKlBIBjBk+z17K fGPufHaraI42OwOSVoQ7IemNSAjPH2dkEncwRw4cAE5bmBQFoJ9ik3JE/UzjYpx6LI/L /XXY+3YZx7OIeDUBuu51n9mj8xE6t4p7ezlkrkBewMrMPO1W+sU+d0HitD6Ci37f/vr1 2Kpm5CVyuxmw83+Ix00+1sWfYAmhbcqt40DSUwhspdB5A1+Ihb4BtBkZ73VAYMZEeige VgOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687821611; x=1690413611; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Wv9Tq5llbl/sjP52djumXiDvzm3itZBu/GStUzP7o5Y=; b=Q/bg1m//hbyKkf8TE5zdTGF/H6Ypmnj7BwgS3oIw80tXz+kD/Badof1kiDS57gQLbT e10SutFIzXxB+8JS2Q7K/BmD2drrxKUHBuIXoqtZq1ZMdtN383+ZOYXHSOxdD/eawiOH gehqQsKdL2JlIj00RCRSq8+nr4bMu0DKty5+p1o+rTmB2xPXRR0fWmpbCtVUcaNwZYqv u9qNo1xUuLdzFU/I7HDnbyKFjj6ED9Rg8Q96jkuKetmmvOmRK6FcroysW0bmbkNyw4aM f2q4smQKlOnBOB25a2H07sCZ2IZ+ZH0vzCIXvjssOTWNoaJgd3IZuqBPXMuCdEVZRCBY zeFw== X-Gm-Message-State: AC+VfDz8ZHTNHy4eBRMa4+wbx9PN7WzxFRhJ4s4Cj0l7Br6sxJ5xAEq8 K+Gc+2VvFS4WhErzNNu454tQ/oUTXNoBaodJi0M= X-Received: by 2002:a17:907:368c:b0:982:2586:f85 with SMTP id bi12-20020a170907368c00b0098225860f85mr25253076ejc.65.1687821610863; Mon, 26 Jun 2023 16:20:10 -0700 (PDT) Received: from m1x-phil.lan ([176.187.199.226]) by smtp.gmail.com with ESMTPSA id ck18-20020a170906c45200b0098e38d2e584sm2599001ejb.43.2023.06.26.16.20.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 26 Jun 2023 16:20:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bin Meng , Liu Zhiwei , =?utf-8?q?Alex_Benn=C3=A9e?= , Thomas Huth , Beraldo Leal , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Palmer Dabbelt , Wainer dos Santos Moschetta , Daniel Henrique Barboza , Weiwei Li , qemu-riscv@nongnu.org Subject: [PATCH 00/16] target/riscv: Allow building without TCG (KVM-only so far) Date: Tue, 27 Jun 2023 01:19:51 +0200 Message-Id: <20230626232007.8933-1-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Hi, this series reorder TCG specific code in order to easily build a KVM-only binary. sysemu specific code is also moved around, to help noticing invalid uses from user emulation. Last patch adds a new job to our CI to avoid this to bitrot. Please review, Phil. Philippe Mathieu-Daudé (16): target/riscv: Remove unused 'instmap.h' header in translate.c target/riscv: Restrict KVM-specific fields from ArchCPU target/riscv: Restrict sysemu specific header to user emulation target/riscv: Restrict 'rv128' machine to TCG accelerator target/riscv: Move sysemu-specific files to target/riscv/sysemu/ target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu target/riscv: Move TCG-specific files to target/riscv/tcg/ target/riscv: Move TCG-specific cpu_get_tb_cpu_state() to tcg/cpu.c target/riscv: Expose some 'trigger' prototypes from debug.c target/riscv: Extract TCG-specific code from debug.c target/riscv: Move sysemu-specific debug files to target/riscv/sysemu/ target/riscv: Expose riscv_cpu_pending_to_irq() from cpu_helper.c target/riscv: Move TCG/sysemu-specific code to tcg/sysemu/cpu_helper.c target/riscv: Move sysemu-specific code to sysemu/cpu_helper.c target/riscv: Restrict TCG-specific prototype declarations gitlab-ci.d/crossbuilds: Add KVM riscv64 cross-build jobs target/riscv/cpu.h | 29 +- target/riscv/internals.h | 4 + target/riscv/{ => sysemu}/debug.h | 6 + target/riscv/{ => sysemu}/instmap.h | 0 target/riscv/{ => sysemu}/kvm_riscv.h | 0 target/riscv/{ => sysemu}/pmp.h | 0 target/riscv/{ => sysemu}/pmu.h | 0 target/riscv/{ => sysemu}/time_helper.h | 0 target/riscv/{ => tcg}/XVentanaCondOps.decode | 0 target/riscv/{ => tcg}/insn16.decode | 0 target/riscv/{ => tcg}/insn32.decode | 0 target/riscv/{ => tcg}/xthead.decode | 0 hw/riscv/virt.c | 2 +- target/riscv/cpu.c | 35 +- target/riscv/cpu_helper.c | 1692 +---------------- target/riscv/csr.c | 6 +- target/riscv/{ => sysemu}/arch_dump.c | 0 target/riscv/sysemu/cpu_helper.c | 863 +++++++++ target/riscv/{ => sysemu}/debug.c | 153 +- target/riscv/{ => sysemu}/kvm-stub.c | 0 target/riscv/{ => sysemu}/kvm.c | 0 target/riscv/{ => sysemu}/machine.c | 8 +- target/riscv/{ => sysemu}/monitor.c | 0 target/riscv/{ => sysemu}/pmp.c | 0 target/riscv/{ => sysemu}/pmu.c | 0 target/riscv/{ => sysemu}/riscv-qmp-cmds.c | 0 target/riscv/{ => sysemu}/time_helper.c | 0 target/riscv/{ => tcg}/bitmanip_helper.c | 0 target/riscv/tcg/cpu.c | 97 + target/riscv/{ => tcg}/crypto_helper.c | 0 target/riscv/{ => tcg}/fpu_helper.c | 0 target/riscv/{ => tcg}/m128_helper.c | 0 target/riscv/{ => tcg}/op_helper.c | 0 target/riscv/tcg/sysemu/cpu_helper.c | 766 ++++++++ target/riscv/tcg/sysemu/debug.c | 165 ++ target/riscv/tcg/tcg-stub.c | 31 + target/riscv/{ => tcg}/translate.c | 1 - target/riscv/{ => tcg}/vector_helper.c | 0 target/riscv/{ => tcg}/zce_helper.c | 0 .gitlab-ci.d/crossbuilds.yml | 8 + target/riscv/meson.build | 33 +- target/riscv/sysemu/meson.build | 14 + target/riscv/tcg/meson.build | 22 + target/riscv/tcg/sysemu/meson.build | 4 + 44 files changed, 2046 insertions(+), 1893 deletions(-) rename target/riscv/{ => sysemu}/debug.h (96%) rename target/riscv/{ => sysemu}/instmap.h (100%) rename target/riscv/{ => sysemu}/kvm_riscv.h (100%) rename target/riscv/{ => sysemu}/pmp.h (100%) rename target/riscv/{ => sysemu}/pmu.h (100%) rename target/riscv/{ => sysemu}/time_helper.h (100%) rename target/riscv/{ => tcg}/XVentanaCondOps.decode (100%) rename target/riscv/{ => tcg}/insn16.decode (100%) rename target/riscv/{ => tcg}/insn32.decode (100%) rename target/riscv/{ => tcg}/xthead.decode (100%) rename target/riscv/{ => sysemu}/arch_dump.c (100%) create mode 100644 target/riscv/sysemu/cpu_helper.c rename target/riscv/{ => sysemu}/debug.c (83%) rename target/riscv/{ => sysemu}/kvm-stub.c (100%) rename target/riscv/{ => sysemu}/kvm.c (100%) rename target/riscv/{ => sysemu}/machine.c (98%) rename target/riscv/{ => sysemu}/monitor.c (100%) rename target/riscv/{ => sysemu}/pmp.c (100%) rename target/riscv/{ => sysemu}/pmu.c (100%) rename target/riscv/{ => sysemu}/riscv-qmp-cmds.c (100%) rename target/riscv/{ => sysemu}/time_helper.c (100%) rename target/riscv/{ => tcg}/bitmanip_helper.c (100%) create mode 100644 target/riscv/tcg/cpu.c rename target/riscv/{ => tcg}/crypto_helper.c (100%) rename target/riscv/{ => tcg}/fpu_helper.c (100%) rename target/riscv/{ => tcg}/m128_helper.c (100%) rename target/riscv/{ => tcg}/op_helper.c (100%) create mode 100644 target/riscv/tcg/sysemu/cpu_helper.c create mode 100644 target/riscv/tcg/sysemu/debug.c create mode 100644 target/riscv/tcg/tcg-stub.c rename target/riscv/{ => tcg}/translate.c (99%) rename target/riscv/{ => tcg}/vector_helper.c (100%) rename target/riscv/{ => tcg}/zce_helper.c (100%) create mode 100644 target/riscv/sysemu/meson.build create mode 100644 target/riscv/tcg/meson.build create mode 100644 target/riscv/tcg/sysemu/meson.build