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[v2,0/9] {tcg,aarch64}: Add TLB_CHECK_ALIGNED

Message ID 20230621121902.1392277-1-richard.henderson@linaro.org
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Series {tcg,aarch64}: Add TLB_CHECK_ALIGNED | expand

Message

Richard Henderson June 21, 2023, 12:18 p.m. UTC 
v1: https://lore.kernel.org/qemu-devel/20230223204342.1093632-1-richard.henderson@linaro.org/

Prerequisites and some of v1 merged since February.
Split TLB_DISCARD_WRITE renumber to a separate patch,
since there are now dependencies in tcg/.


r~


Richard Henderson (9):
  accel/tcg: Store some tlb flags in CPUTLBEntryFull
  accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK
  accel/tcg: Renumber TLB_DISCARD_WRITE
  target/arm: Support 32-byte alignment in pow2_align
  exec/memattrs: Remove target_tlb_bit*
  accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull
  accel/tcg: Add TLB_CHECK_ALIGNED
  target/arm: Do memory type alignment check when translation disabled
  target/arm: Do memory type alignment check when translation enabled

 include/exec/cpu-all.h     |  29 ++++++--
 include/exec/cpu-defs.h    |   9 +++
 include/exec/memattrs.h    |  12 ----
 accel/tcg/cputlb.c         | 142 +++++++++++++++++++++++++------------
 target/arm/ptw.c           |  28 ++++++++
 target/arm/tcg/hflags.c    |  34 ++++++++-
 target/arm/tcg/translate.c |   8 +--
 target/sparc/mmu_helper.c  |   2 +-
 tcg/tcg-op-ldst.c          |   2 +-
 9 files changed, 190 insertions(+), 76 deletions(-)