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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y17-20020a1c4b11000000b003f7298a32ccsm12195508wma.41.2023.06.06.03.46.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 03:46:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Beniamino Galvani , Strahinja Jankovic , Guenter Roeck , qemu-stable@nongnu.org, Michael Tokarev Subject: [PATCH 0/2] allwinner-a10: Fix interrupt controller regression Date: Tue, 6 Jun 2023 11:46:07 +0100 Message-Id: <20230606104609.3692557-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit 2c5fa0778c3b430 we fixed an endianness bug in the Allwinner A10 PIC model; however in the process we introduced a regression. This is because the old code was robust against the incoming 'level' argument being something other than 0 or 1, whereas the new code was not. In particular, the allwinner-sdhost code treats its IRQ line as 0-vs-non-0 rather than 0-vs-1, so when the SD controller set its IRQ line for any reason other than transmit the interrupt controller would ignore it. The observed effect was a guest timeout when rebooting the guest kernel. Patch 1 in this series fixes the regression by restoring the old behaviour of aw_a10_pic_set_irq() for non-0 levels; it is stable material. Patch 2 changes the SD controller to follow our usual convention that simple IRQ lines only send 0 or 1; this isn't strictly necessary with patch 1, but it avoids future surprises. It doesn't need to go to stable. thanks -- PMM Peter Maydell (2): hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1 hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels hw/intc/allwinner-a10-pic.c | 2 +- hw/sd/allwinner-sdhost.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé