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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 8-20020a05600c22c800b003ef71d541cbsm4673752wmg.1.2023.04.14.09.04.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:04:14 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 0/3] target/arm: Fix handling of VSTCR_EL2.SW and VTCR_EL2.NSW Date: Fri, 14 Apr 2023 17:04:10 +0100 Message-Id: <20230414160413.549801-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When FEAT_SEL2 (secure EL2) is implemented, the bits VSTCR_EL2.SW and VTCR_EL2.NSW allow the guest to set things up so that the stage 2 walk for an IPA is done to the other address space, eg * a stage 2 walk for an NS IPA done to secure physical memory (where the translation table base address and other parameters for the walk come from the NS control registers VTTBR_EL2 and VTCR_EL2) * a stage 2 walk for an S IPA done to non-secure physical memory (where the parameters from the walk come from the S control registers VSTTBR_EL2 and VSTCR_EL2) We tried to implement this, but didn't get it right -- in get_phys_addr_twostage() we identify whether we need to do the s2 walk in Secure or NonSecure, but then we fail to pay attention to whether we were doing the walk for an NS or S IPA. The fix for this is simple -- set ptw->in_mmu_idx and ptw->in_secure based on ipa_secure, with only ptw->in_ptw_idx depending on s2walk_secure. However to make this work we first need to fix a couple of places in the ptw code that were incorrectly looking at ptw->in_secure when they either should not be or should be doing something based on ptw->in_ptw_idx. This fixes https://gitlab.com/qemu-project/qemu/-/issues/1600 . NB: I have tested that this fixes the test case in the bug, and that it doesn't break 'make check-avocado', but I don't have a huge supply of EL2-using guests to hand so the patchset hasn't received exhaustive testing. Plus this area of the architecture and this bit of QEMU's codebase are pretty hairy -- so careful review would be a good idea :-) thanks -- PMM Peter Maydell (3): target/arm: Don't allow stage 2 page table walks to downgrade to NS target/arm: Set ptw->out_secure correctly for stage 2 translations target/arm: handle ipa_secure vs s2walk_secure correctly target/arm/ptw.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-)