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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH for-8.1 00/42] tcg: Simplify calls to load/store helpers Date: Fri, 7 Apr 2023 19:42:31 -0700 Message-Id: <20230408024314.3357414-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org There are several changes to the load/store helpers coming, and making sure that those changes are properly reflected across all of the backends was harrowing. I have gone back and restarted by hoisting the code out of the backends and into tcg.c. We already have all of the parameters for the host function call abi for "normal" helpers, we simply need to apply that to the load/store slow path. Unlike the normal helpers, we cannot use tcg_gen_foo(), so we start by creating additional required backend primitives for extension. This is followed by putting them together with knowledge of the types, and some functions to handle register move/extend with overlap. Finally, top-level tcg_out_{ld,st}_helper_args which contains all knowledge of the helper function signatures. There will be additional backend unification coming for user-only, and for sparc64, but that needs to wait for some of the changes within my atomicity patch set. And this is quite large enough for now. One final note about patch 27, dropping support for riscv32 as a host. This is driven by the existing /* We don't support oversize guests */ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); which causes the build to fail for all 64-bit guests. One of the upcoming changes is to build TCG once, which means that the build would fail entirely. Which means we might as well drop it entirely. Doing this first simplifies everything else. I have not yet simplified top-level meson.build to match, because I don't know if we should leave something to support riscv32 with --enable-tcg-interpreter. I first reaction is no, because there really is no way to test it, because no one ships such an OS. r~ Richard Henderson (42): tcg: Replace if + tcg_abort with tcg_debug_assert tcg: Replace tcg_abort with g_assert_not_reached tcg: Split out tcg_out_ext8s tcg: Split out tcg_out_ext8u tcg: Split out tcg_out_ext16s tcg: Split out tcg_out_ext16u tcg: Split out tcg_out_ext32s tcg: Split out tcg_out_ext32u tcg: Split out tcg_out_exts_i32_i64 tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 tcg/mips: Conditionalize tcg_out_exts_i32_i64 tcg/riscv: Conditionalize tcg_out_exts_i32_i64 tcg: Split out tcg_out_extu_i32_i64 tcg/i386: Conditionalize tcg_out_extu_i32_i64 tcg: Split out tcg_out_extrl_i64_i32 tcg: Introduce tcg_out_movext tcg: Introduce tcg_out_xchg tcg: Introduce tcg_out_movext2 tcg: Clear TCGLabelQemuLdst on allocation tcg/i386: Use TCGType not bool is_64 in tcg_out_qemu_{ld,st} tcg/aarch64: Rename ext to d_type in tcg_out_qemu_ld tcg/aarch64: Pass TGType to tcg_out_qemu_st tcg/arm: Use TCGType not bool is_64 in tcg_out_qemu_{ld,st} tcg/i386: Use TCGType not bool is_64 in tcg_out_qemu_{ld,st} tcg/ppc: Use TCGType not bool is_64 in tcg_out_qemu_{ld,st} tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st} tcg/riscv: Require TCG_TARGET_REG_BITS == 64 tcg/riscv: Expand arguments to tcg_out_qemu_{ld,st} tcg: Move TCGLabelQemuLdst to tcg.c tcg: Introduce tcg_out_ld_helper_args tcg: Introduce tcg_out_st_helper_args tcg/loongarch64: Simplify constraints on qemu_ld/st tcg/mips: Reorg tcg_out_tlb_load tcg/mips: Simplify constraints on qemu_ld/st tcg/ppc: Reorg tcg_out_tlb_read tcg/ppc: Adjust constraints on qemu_ld/st tcg/ppc: Remove unused constraints A, B, C, D tcg/riscv: Simplify constraints on qemu_ld/st tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st tcg/s390x: Simplify constraints on qemu_ld/st tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} include/tcg/tcg.h | 6 - tcg/loongarch64/tcg-target-con-set.h | 2 - tcg/loongarch64/tcg-target-con-str.h | 1 - tcg/mips/tcg-target-con-set.h | 13 +- tcg/mips/tcg-target-con-str.h | 2 - tcg/ppc/tcg-target-con-set.h | 11 +- tcg/ppc/tcg-target-con-str.h | 6 - tcg/riscv/tcg-target-con-set.h | 8 - tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target.h | 22 +- tcg/s390x/tcg-target-con-set.h | 2 - tcg/s390x/tcg-target-con-str.h | 1 - target/i386/tcg/translate.c | 20 +- target/s390x/tcg/translate.c | 4 +- tcg/optimize.c | 10 +- tcg/tcg.c | 556 ++++++++++++++++++++++++++- tcg/aarch64/tcg-target.c.inc | 156 ++++---- tcg/arm/tcg-target.c.inc | 242 ++++-------- tcg/i386/tcg-target.c.inc | 257 +++++-------- tcg/loongarch64/tcg-target.c.inc | 167 +++----- tcg/mips/tcg-target.c.inc | 392 ++++++++----------- tcg/ppc/tcg-target.c.inc | 319 +++++++-------- tcg/riscv/tcg-target.c.inc | 347 ++++++----------- tcg/s390x/tcg-target.c.inc | 243 +++++------- tcg/sparc64/tcg-target.c.inc | 125 +++--- tcg/tcg-ldst.c.inc | 15 +- tcg/tci/tcg-target.c.inc | 116 +++++- 27 files changed, 1596 insertions(+), 1448 deletions(-)