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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l12-20020a5d560c000000b002cfe685bfd6sm2339831wrv.108.2023.03.31.07.50.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 07:50:46 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/3] target/arm: Fix ESR_EL2 buglet, implement FEAT_PAN3 Date: Fri, 31 Mar 2023 15:50:42 +0100 Message-Id: <20230331145045.2584941-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The main purpose of this patchset is to implement FEAT_PAN3, which allows the guest to force privileged code to not be able to access memory that can be executed by user code. (This is an extension of the existing FEAT_PAN which denies access if user code could read or write the memory.) That is all done in patch 3. Patches 1 and 2 fix a buglet in our ESR_EL2 syndrome reporting that I happened to notice while testing the FEAT_PAN3 code: we were reporting the detailed instruction syndrome information for all data aborts reported to EL2, whereas the architecture requires this to happen only for stage-2 aborts, not stage-1 aborts. This is all for-8.1 material -- the syndrome bug is minor and has been around forever so isn't worth trying to fix for 8.0 at this point in the release cycle. thanks -- PMM Peter Maydell (3): target/arm: Pass ARMMMUFaultInfo to merge_syn_data_abort() target/arm: Don't set ISV when reporting stage 1 faults in ESR_EL2 target/arm: Implement FEAT_PAN3 docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 2 +- target/arm/ptw.c | 14 +++++++++++++- target/arm/tcg/tlb_helper.c | 26 ++++++++++++++++---------- 5 files changed, 36 insertions(+), 12 deletions(-)