From patchwork Tue Jan 10 16:43:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 640853 Delivered-To: patch@linaro.org Received: by 2002:a17:522:f3c4:b0:4b4:3859:abed with SMTP id in4csp2829851pvb; Tue, 10 Jan 2023 09:34:42 -0800 (PST) X-Google-Smtp-Source: AMrXdXvXMV+H+L/9dCw8WAZ4V6YKi59AkO0SB5RMdJ5WGMy+iXSj0uTVe3FOG4YgZLSSzvq90+si X-Received: by 2002:ac8:74cc:0:b0:3a5:306f:b124 with SMTP id j12-20020ac874cc000000b003a5306fb124mr93909498qtr.10.1673372082664; Tue, 10 Jan 2023 09:34:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673372082; cv=none; d=google.com; s=arc-20160816; b=hVI/4c9JB7lA92YU0d2kNzMsWBxx77Ums64a6PjDa1t4lqim9UifOxdjrTSouvar/D uDp7InvICCxCDOAQFXBRL8GMSrzcGtR/qOZtPilEp16Fm3bGBxfxj/0O5SiOF8daKcRd IWWr4rEX22xR8oQHOmr6a9J92K4ABNS2ng174S52kRguhPuvBTl8M+dSDF2qO04t8L8r L5ztTevVnBuep3mVsUPTKVZDM/1+GLb3UbcgN5S9gZNemV74hs0c68H2SwTokWykApZa CHDECekNZMYvYT+Ox9cI4dfMVlUukj2wknLrrDZzrZKUWq6agaDBNB+5qZ5ZbwbQ4/Ji FI5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature; bh=CPwog7s6qoO9BZW8ROM2vT1B0KSgnjrgal2QWFXh9rY=; b=gdPxLltBSZAewhxPYp+Q/S+DMHjl3068r+hk08A2zivieYOT4o2xU39chHkAfs292b RLO7DOPHsUsbhNz4dI8T4ZU5gpmbZ/r0LGKfY47N/XKD5GKFC8EVNaTwJ3DLzU4hNDB+ XAOrlRxZ6OEyOIk5/RaL72v6Ul1B0qAwt3k919+Pv1lOef75ooZCAYYhhHPmva1zweOL 5BG7/LwPJEt596CNJ5FdAge2S4RDoo7x+2GpbnjsPMqYH6D4WLW9cZeWvOFW5bCp+odC h+v9rvrgn05McnfUzizxmw683rEIhpLtyeiEKXni6q9uTuZBVuaT1EuMZIvzvNta0F58 cAHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="AGJDF0/S"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s24-20020ac87598000000b003a7eafc9304si6675840qtq.42.2023.01.10.09.34.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Jan 2023 09:34:42 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="AGJDF0/S"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFHjX-0003nj-2F; Tue, 10 Jan 2023 11:44:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFHjS-0003iO-JD for qemu-devel@nongnu.org; Tue, 10 Jan 2023 11:44:14 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFHjQ-000670-2S for qemu-devel@nongnu.org; Tue, 10 Jan 2023 11:44:13 -0500 Received: by mail-wr1-x435.google.com with SMTP id d17so12433012wrs.2 for ; Tue, 10 Jan 2023 08:44:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=CPwog7s6qoO9BZW8ROM2vT1B0KSgnjrgal2QWFXh9rY=; b=AGJDF0/SUFvufs1KEMv/KU+dp1USHFJlRTapZjtO7A2qyyMYd3LSwiz0z+CHHSGbok l0aaswSGgU12VI0HRB0ZVa9v8t5xDbrI2JT0o6xCfGqZI7RsmmlZno7ixVzwe6sJ1H6F OE/njecxvVUKH/pM0Tv5d0bKvCxCLL+jzato49dThhQCzSeQwz5Ewupx9Eu/U3sMgNBR d3+WWqmfh702tbR1qwTgkIVOgDVEHW64jPUp83jICNVeqnCKCjSoPiRV6iqkDpUCv1UH sSsVoHTLBmHhc26Bk/+cJ0dHTw1oGhy3kTguPsqt+w5MP5v35tytGIJDauHbrVN3qnvS g7xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=CPwog7s6qoO9BZW8ROM2vT1B0KSgnjrgal2QWFXh9rY=; b=Uyd9WVd7YESj9Twzol6yP29euqahGqFzHUQBcm5dCcvRc/ELRM12U4B9gWx7XsZGjJ bBArHWJ4YF+6QId/T2UDeBTfHQqj64zg1MYI6O+sv4Pb92dpt2oXcbAMmj+cQvRFA99A X6ACqctotW6mTlh4EFf+GUK+VhTYbzTTbiEqpODIgpY6okNSene1a1vwQ6tpgLe30yfy +uWfDpXJISsdgRrPxR/snN0KODu0hs7B98DsTE/uZuFcZeSTZWFgchPgnXdOfoexH60x zIE/HUqbRj1k1P7Rqe99f9FvhzjkncKsYFRoMQ2WaqkOpDaQGXnFQArRhu8cDiamq6uH FrPw== X-Gm-Message-State: AFqh2koEFFTEa5XeOSomtL4hx9Ukn8rMUO+vCEnAA5+cjceGv5i6DlGy gtAH9q1yoEHAPPlLg+Rtd4wkkYgBqWJEP8Gh X-Received: by 2002:a05:6000:148:b0:2bb:dc79:17dc with SMTP id r8-20020a056000014800b002bbdc7917dcmr7276080wrx.19.1673369050311; Tue, 10 Jan 2023 08:44:10 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id z18-20020a5d44d2000000b002368f6b56desm13995150wrr.18.2023.01.10.08.44.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Jan 2023 08:44:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: ale@rev.ng, Andrey Smirnov , Thomas Huth , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Niek Linnenbank , Jean-Christophe Dubois , Antonio Caggiano , Rob Herring , Antony Pavlov , Jan Kiszka , Beniamino Galvani Subject: [PATCH 00/18] hw/arm: Move various objects to softmmu_ss to build them once (part 1) Date: Tue, 10 Jan 2023 17:43:48 +0100 Message-Id: <20230110164406.94366-1-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Hi, This series unifies various objects from libqemu-arm-softmmu.fa.p and libqemu-aarch64-softmmu.fa.p into libcommon.fa.p. So instead of building each object twice, one for 32-bit ARM ARM and another for 64-bit Aarch64, hardware-related objects are built once. Part #1 is the low hanging fruits :) Also I cut the series under 20 patches to ease review digestion. The overall logic is to only access ARMCPU as opaque pointer when possible. This way we don't depend on the (target/arm/) "cpu.h" header which contains target-specific definitions and forces units to be added in Meson's arm_ss[] specific source set. In order to reduce use of "target/arm/cpu.h" by hardware units, we split the hardware-facing definitions in the new "hw/arm/cpu.h" header. Finally, instead of using object_initialize() on the full ARMCPU variable, we use object_new(TYPE ARM_CPU). Since QOM types are registered with their class/instance size, we don't need to provide sizeof(ARMCPU) to allocate the object. Please review, Phil. Based-on: <20230109115316.2235-1-philmd@linaro.org> "hw/arm: Cleanups before pflash refactor" Philippe Mathieu-Daudé (18): hw/arm: Move various units to softmmu_ss[] hw/arm/boot: Include missing 'exec/cpu-all.h' header target/arm/cpregs: Include missing 'target/arm/cpu.h' header hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h" target/arm: Move CPU QOM type definitions to "hw/arm/cpu.h" target/arm: Move CPU definitions consumed by HW model to "hw/arm/cpu.h" hw/arm: Move more units to softmmu_ss[] hw/arm: Move units to softmmu[] by replacing "{target -> hw}/arm/cpu.h" hw/arm/armv7m: Remove 'target/arm/cpu.h' from NVIC header hw/arm: Move various armv7m-related units to softmmu_ss[] hw/arm/digic: Remove unnecessary target_long use hw/arm/digic: Replace object_initialize(ARMCPU) by object_new(ARMCPU) hw/arm/fsl-imx: Correct GPIO/GPT index in QOM tree hw/arm/fsl-imx25: Replace object_initialize(ARMCPU) by object_new() hw/arm/fsl-imx31: Replace object_initialize(ARMCPU) by object_new() hw/arm/fsl-imx7: Replace object_initialize(ARMCPU) by object_new() hw/arm/fsl-imx6: Replace object_initialize(ARMCPU) by object_new() hw/arm/allwinner: Replace object_initialize(ARMCPU) by object_new() hw/arm/allwinner-a10.c | 10 ++-- hw/arm/allwinner-h3.c | 14 +++--- hw/arm/armv7m.c | 2 + hw/arm/boot.c | 1 + hw/arm/collie.c | 1 - hw/arm/cubieboard.c | 2 +- hw/arm/digic.c | 7 +-- hw/arm/digic_boards.c | 2 +- hw/arm/fsl-imx25.c | 9 ++-- hw/arm/fsl-imx31.c | 9 ++-- hw/arm/fsl-imx6.c | 14 +++--- hw/arm/fsl-imx6ul.c | 12 ++--- hw/arm/fsl-imx7.c | 10 ++-- hw/arm/gumstix.c | 1 - hw/arm/highbank.c | 2 +- hw/arm/imx25_pdk.c | 2 +- hw/arm/integratorcp.c | 2 +- hw/arm/kzm.c | 2 +- hw/arm/mainstone.c | 2 +- hw/arm/mcimx6ul-evk.c | 2 +- hw/arm/mcimx7d-sabre.c | 2 +- hw/arm/meson.build | 83 ++++++++++++++++++---------------- hw/arm/musicpal.c | 2 +- hw/arm/omap_sx1.c | 1 - hw/arm/palm.c | 2 +- hw/arm/sabrelite.c | 2 +- hw/arm/spitz.c | 2 +- hw/arm/strongarm.c | 2 +- hw/arm/z2.c | 1 - include/hw/arm/allwinner-a10.h | 4 +- include/hw/arm/allwinner-h3.h | 4 +- include/hw/arm/cpu.h | 77 +++++++++++++++++++++++++++++++ include/hw/arm/digic.h | 4 +- include/hw/arm/fsl-imx25.h | 4 +- include/hw/arm/fsl-imx31.h | 4 +- include/hw/arm/fsl-imx6.h | 4 +- include/hw/arm/fsl-imx6ul.h | 4 +- include/hw/arm/fsl-imx7.h | 4 +- include/hw/intc/armv7m_nvic.h | 2 +- target/arm/cpregs.h | 2 + target/arm/cpu-qom.h | 28 +----------- target/arm/cpu.h | 42 ++--------------- 42 files changed, 205 insertions(+), 181 deletions(-) create mode 100644 include/hw/arm/cpu.h