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[209.51.188.17]) by mx.google.com with ESMTPS id t22-20020ac87396000000b003445b710d98si2403619qtp.350.2022.12.10.07.56.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 10 Dec 2022 07:56:04 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="hdciz/TS"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p42CF-0003Pu-LK; Sat, 10 Dec 2022 10:55:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p42C1-0003I4-14 for qemu-devel@nongnu.org; Sat, 10 Dec 2022 10:55:15 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p42By-0004D3-CD for qemu-devel@nongnu.org; Sat, 10 Dec 2022 10:55:12 -0500 Received: by mail-wr1-x431.google.com with SMTP id w15so7983894wrl.9 for ; Sat, 10 Dec 2022 07:55:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=FCfMHe5b/hTNsGMUHYdZCTbKXqMgLewG0q+mJCK5/VM=; b=hdciz/TS/f8YyUvEWDBsN+hdTpvIzipJEuixF0SIaANHUFmA/62cntDL1TgUbktiZ8 tMY9+Km7IJqS9GhDOinpBhoE2zNsjG1rOqFnwp6Wu841NmAwilTVfYCjZYviFDRrVGBY ND46TjeJEOjEYSD/3qqerZ55qxO9PO0DjXaypnuk/jB2sHVr6ksPdclHbWyEBVpW4QOo qW0XrHZAJnkfLKaL6pntHRrnBigsKTqMdsfKpQWBnyF7bpUuyh6Kh/BrLeWxAxgmp3P0 gy0JT9xIn9JZCv5HjmvPHhWngu9LqwZyRf3PD/fC+IqZHNOJEM9C8Mgdd7GysBaOGFIa EFOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=FCfMHe5b/hTNsGMUHYdZCTbKXqMgLewG0q+mJCK5/VM=; b=D1pgYbbdVu3E+voJ2FKdRA3It94IxmdpvUB+PFjK1GLALwj+DWDgu2DwshUCIOgaIl RuXb6IpGm/2AuDxGgJmn3C3E4yUhHckFxW8GCoFujuQux726PErSGuZa6X2tz8rhcE8H 1gVplUG+0N9gPydVwioItsQkELQ3LhUoqTzAIE/SUo5ub/+Mw4wU5BtIWZD4zF7ajdzg KcMvJSFWvFAWMw+Oxa1AxUMDLZ6NQc/XmDULi2aIZbf5HAg8uSPS9ISzqlgctILZg7G8 EF+WH4MAxVEnWBo/tv2l5ezrFnv/IvUUFlYyCfVA9HcCRUCaaB7Bf7v2wgObGFwFZUeB Z2NQ== X-Gm-Message-State: ANoB5pkJVFz71AHZNv8Ap7NyI/MueqBL7ZcHK0V5zK7hcd66cMmEugMo OVLmTwOBijxakqdwDcr+4uT5jQw+LKvvLpiR1Ik= X-Received: by 2002:a5d:490d:0:b0:242:fa5:ce83 with SMTP id x13-20020a5d490d000000b002420fa5ce83mr7989559wrq.37.1670687705218; Sat, 10 Dec 2022 07:55:05 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id w18-20020adfee52000000b00236883f2f5csm4179435wro.94.2022.12.10.07.55.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 10 Dec 2022 07:55:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Milica Lazarevic , Dragan Mladjenovic , Aurelien Jarno , Djordje Todorovic , Jiaxun Yang , Bernhard Beschow Subject: [PATCH-for-8.0 0/7] hw/mips/malta: Generate nanoMIPS bootloader with bootloader generator API Date: Sat, 10 Dec 2022 16:54:55 +0100 Message-Id: <20221210155502.74609-1-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Bernhard posted his "Consolidate PIIX south bridges" v3 series: https://lore.kernel.org/qemu-devel/20221204190553.3274-1-shentey@gmail.com/ However in order to simplify it, on the Malta board we need to set the PIIX IRQC[A:D] routing values via the embedded bootloader (used when no external BIOS is provided). Jiaxun added a "bootloader generator API" for 32-bit wide instructions, and we use it in the write_bootloader() function. This series provides the nanoMIPS equivalent generated instructions and update the write_bootloader_nanomips() function. That allow fixing the TODO left in https://lore.kernel.org/qemu-devel/20221027204720.33611-3-philmd@linaro.org/ and apply Bernhard's consolidation. Please review, Phil. Philippe Mathieu-Daudé (7): hw/mips/bootloader: Handle buffers as opaque arrays hw/mips/bootloader: Pass 32-bit immediate value to LUI opcode generator hw/mips/bootloader: Implement nanoMIPS NOP opcode hw/mips/bootloader: Implement nanoMIPS LUI opcode hw/mips/bootloader: Implement nanoMIPS SW opcode hw/mips/bootloader: Implement nanoMIPS SW opcode hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs hw/mips/bootloader.c | 140 +++++++++++++++++++++++------ hw/mips/malta.c | 167 ++++++++++------------------------- include/hw/mips/bootloader.h | 10 +-- 3 files changed, 162 insertions(+), 155 deletions(-)