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([2806:102e:18:2efc:d298:de6f:2ed:87a4]) by smtp.gmail.com with ESMTPSA id s14-20020a05683004ce00b0066f7e1188f0sm53531otd.68.2022.12.08.18.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 18:05:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v4 00/27] tcg/s390x: misc patches Date: Thu, 8 Dec 2022 20:05:03 -0600 Message-Id: <20221209020530.396391-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Based-on: 20221202053958.223890-1-richard.henderson@linaro.org ("[PATCH for-8.0 v3 00/34] tcg misc patches") Changes from v3: * Require z196 as minimum cpu -- 6 new patches removing checks. * Tighten constraints on AND, OR, XOR, CMP, trying get the register allocator to hoist things that can't be done in a single insn. * Avoid the constant pool for movi. I believe that I have addressed all of the discussion in v3, except perhaps for goto_tb concurrent modifications to jumps. I'm still not quite sure what to do about that. r~ Richard Henderson (27): tcg/s390x: Use register pair allocation for div and mulu2 tcg/s390x: Remove TCG_REG_TB tcg/s390x: Always set TCG_TARGET_HAS_direct_jump tcg/s390x: Remove USE_LONG_BRANCHES tcg/s390x: Check for long-displacement facility at startup tcg/s390x: Check for extended-immediate facility at startup tcg/s390x: Check for general-instruction-extension facility at startup tcg/s390x: Check for load-on-condition facility at startup tcg/s390x: Remove FAST_BCR_SER facility check tcg/s390x: Remove DISTINCT_OPERANDS facility check tcg/s390x: Use LARL+AGHI for odd addresses tcg/s390x: Distinguish RRF-a and RRF-c formats tcg/s390x: Distinguish RIE formats tcg/s390x: Support MIE2 multiply single instructions tcg/s390x: Support MIE2 MGRK instruction tcg/s390x: Issue XILF directly for xor_i32 tcg/s390x: Tighten constraints for or_i64 and xor_i64 tcg/s390x: Tighten constraints for and_i64 tcg/s390x: Support MIE3 logical operations tcg/s390x: Create tgen_cmp2 to simplify movcond tcg/s390x: Generalize movcond implementation tcg/s390x: Support SELGR instruction in movcond tcg/s390x: Use tgen_movcond_int in tgen_clz tcg/s390x: Implement ctpop operation tcg/s390x: Tighten constraints for 64-bit compare tcg/s390x: Cleanup tcg_out_movi tcg/s390x: Avoid the constant pool in tcg_out_movi tcg/s390x/tcg-target-con-set.h | 18 +- tcg/s390x/tcg-target-con-str.h | 11 +- tcg/s390x/tcg-target.h | 54 +- tcg/s390x/tcg-target.c.inc | 1251 ++++++++++++++++---------------- 4 files changed, 668 insertions(+), 666 deletions(-)