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([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id d12-20020a170903230c00b00186f0f59c85sm4637075plh.235.2022.12.01.21.39.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 21:39:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-8.0 v3 00/34] tcg misc patches Date: Thu, 1 Dec 2022 21:39:24 -0800 Message-Id: <20221202053958.223890-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This contains a few bits that I've queued for 8.0, as well as the first half of the TCGv_i128 patch set (just prior to the introduction of TCG_TYPE_I128). Included are the paired register patches, which have seen changes since v2, and a bit more testing on s390x host (which uses register pairs for multiply and divide, so good testing of the feature without having to bring in all of the other target/ changes for TCGv_i128). Patches lacking review: 04-tcg-Cleanup-trailing-whitespace.patch 05-tcg-Fix-tcg_reg_alloc_dup.patch 06-tcg-Centralize-updates-to-reg_to_temp.patch 07-tcg-Remove-check_regs.patch 09-tcg-Introduce-paired-register-allocation.patch 11-accel-tcg-Set-cflags_next_tb-in-cpu_common_initfn.patch 12-target-sparc-Avoid-TCGV_-LOW-HIGH.patch 15-tcg-Simplify-calls-to-temp_sync-vs-mem_coherent.patch 23-accel-tcg-plugin-Don-t-search-for-the-function-po.patch 27-tcg-Vary-the-allocation-size-for-TCGOp.patch 29-tcg-Reorg-function-calls.patch 30-tcg-Convert-typecode_to_ffi-from-array-to-functio.patch 31-tcg-Factor-init_ffi_layouts-out-of-tcg_context_in.patch 32-tcg-Move-ffi_cif-pointer-into-TCGHelperInfo.patch 33-tcg-aarch64-Merge-tcg_out_callr-into-tcg_out_call.patch r~ Mark Cave-Ayland (1): tcg: convert tcg/README to rst Philippe Mathieu-Daudé (3): tcg/s390x: Fix coding style tcg: Convert typecode_to_ffi from array to function tcg: Factor init_ffi_layouts() out of tcg_context_init() Richard Henderson (30): meson: Move CONFIG_TCG_INTERPRETER to config_host tcg: Cleanup trailing whitespace tcg: Fix tcg_reg_alloc_dup* tcg: Centralize updates to reg_to_temp tcg: Remove check_regs tcg: Tidy tcg_reg_alloc_op tcg: Introduce paired register allocation tcg: Remove TCG_TARGET_STACK_GROWSUP accel/tcg: Set cflags_next_tb in cpu_common_initfn target/sparc: Avoid TCGV_{LOW,HIGH} tcg: Move TCG_{LOW,HIGH} to tcg-internal.h tcg: Add temp_subindex to TCGTemp tcg: Simplify calls to temp_sync vs mem_coherent tcg: Allocate TCGTemp pairs in host memory order tcg: Move TCG_TYPE_COUNT outside enum tcg: Introduce tcg_type_size tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64 tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32 tcg: Use TCG_CALL_ARG_EVEN for TCI special case accel/tcg/plugin: Don't search for the function pointer index accel/tcg/plugin: Avoid duplicate copy in copy_call accel/tcg/plugin: Use copy_op in append_{udata,mem}_cb tci: MAX_OPC_PARAM_IARGS is no longer used tcg: Vary the allocation size for TCGOp tcg: Use output_pref wrapper function tcg: Reorg function calls tcg: Move ffi_cif pointer into TCGHelperInfo tcg/aarch64: Merge tcg_out_callr into tcg_out_call tcg: Add TCGHelperInfo argument to tcg_out_call docs/devel/atomics.rst | 2 + docs/devel/index-tcg.rst | 1 + docs/devel/tcg-ops.rst | 941 +++++++++++++++++ docs/devel/tcg.rst | 2 +- meson.build | 4 +- include/exec/helper-head.h | 2 +- include/tcg/tcg-op.h | 35 +- include/tcg/tcg.h | 96 +- tcg/aarch64/tcg-target.h | 4 +- tcg/arm/tcg-target.h | 4 +- tcg/i386/tcg-target.h | 2 + tcg/loongarch64/tcg-target.h | 3 +- tcg/mips/tcg-target.h | 4 +- tcg/riscv/tcg-target.h | 7 +- tcg/s390x/tcg-target.h | 3 +- tcg/sparc64/tcg-target.h | 3 +- tcg/tcg-internal.h | 58 +- tcg/tci/tcg-target.h | 7 + accel/tcg/plugin-gen.c | 54 +- hw/core/cpu-common.c | 1 + target/sparc/translate.c | 21 +- tcg/optimize.c | 10 +- tcg/tcg-op-vec.c | 10 +- tcg/tcg-op.c | 49 +- tcg/tcg.c | 1655 +++++++++++++++++++----------- tcg/tci.c | 1 - tcg/aarch64/tcg-target.c.inc | 19 +- tcg/arm/tcg-target.c.inc | 10 +- tcg/i386/tcg-target.c.inc | 5 +- tcg/loongarch64/tcg-target.c.inc | 7 +- tcg/mips/tcg-target.c.inc | 3 +- tcg/ppc/tcg-target.c.inc | 36 +- tcg/riscv/tcg-target.c.inc | 7 +- tcg/s390x/tcg-target.c.inc | 32 +- tcg/sparc64/tcg-target.c.inc | 3 +- tcg/tci/tcg-target.c.inc | 7 +- tcg/README | 784 -------------- 37 files changed, 2259 insertions(+), 1633 deletions(-) create mode 100644 docs/devel/tcg-ops.rst delete mode 100644 tcg/README