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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f14-20020a05600c154e00b003c6f3e5ba42sm6212559wmg.46.2022.11.24.03.50.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Nov 2022 03:50:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Taylor Simpson , Song Gao , Xiaojuan Yang , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Bin Meng , Yoshinori Sato , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH for-8.0 00/19] Convert most CPU classes to 3-phase reset Date: Thu, 24 Nov 2022 11:50:03 +0000 Message-Id: <20221124115023.2437291-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This patchset converts the TYPE_CPU base class and most subclasses to use 3-phase reset. (The exception is s390, which is doing something a bit odd with its reset, so the conversion there isn't going to be simple like these others. So I'll do that one separately.) The rationale here is that we should be able to get rid of all the remaining uses of device_class_set_parent_reset() and remove/simplify some of the transitional code that's currently bridging between "legacy" reset and 3-phase reset. NB: even with this series, it's not possible to usefully do anything requiring 3-phase reset of a CPU yet, because all CPU objects get ad-hoc reset by some code somewhere doing a cpu_reset() call on them, which will just do all 3 phases in order. I would like to try to address that eventually, but it's not trivial. thanks -- PMM Peter Maydell (19): hw/core/cpu-common: Convert TYPE_CPU class to 3-phase reset target/arm: Convert to 3-phase reset target/avr: Convert to 3-phase reset target/cris: Convert to 3-phase reset target/hexagon: Convert to 3-phase reset target/i386: Convert to 3-phase reset target/loongarch: Convert to 3-phase reset target/m68k: Convert to 3-phase reset target/microblaze: Convert to 3-phase reset target/mips: Convert to 3-phase reset target/nios2: Convert to 3-phase reset target/openrisc: Convert to 3-phase reset target/ppc: Convert to 3-phase reset target/riscv: Convert to 3-phase reset target/rx: Convert to 3-phase reset target/sh4: Convert to 3-phase reset target/sparc: Convert to 3-phase reset target/tricore: Convert to 3-phase reset target/xtensa: Convert to 3-phase reset target/arm/cpu-qom.h | 4 ++-- target/avr/cpu-qom.h | 4 ++-- target/cris/cpu-qom.h | 4 ++-- target/hexagon/cpu.h | 2 +- target/i386/cpu-qom.h | 4 ++-- target/loongarch/cpu.h | 4 ++-- target/m68k/cpu-qom.h | 4 ++-- target/microblaze/cpu-qom.h | 4 ++-- target/mips/cpu-qom.h | 4 ++-- target/nios2/cpu.h | 4 ++-- target/openrisc/cpu.h | 4 ++-- target/ppc/cpu-qom.h | 4 ++-- target/riscv/cpu.h | 4 ++-- target/rx/cpu-qom.h | 4 ++-- target/sh4/cpu-qom.h | 4 ++-- target/sparc/cpu-qom.h | 4 ++-- target/tricore/cpu-qom.h | 2 +- target/xtensa/cpu-qom.h | 4 ++-- hw/core/cpu-common.c | 7 ++++--- target/arm/cpu.c | 13 +++++++++---- target/avr/cpu.c | 13 +++++++++---- target/cris/cpu.c | 12 ++++++++---- target/hexagon/cpu.c | 12 ++++++++---- target/i386/cpu.c | 12 ++++++++---- target/loongarch/cpu.c | 12 ++++++++---- target/m68k/cpu.c | 12 ++++++++---- target/microblaze/cpu.c | 12 ++++++++---- target/mips/cpu.c | 12 ++++++++---- target/nios2/cpu.c | 12 ++++++++---- target/openrisc/cpu.c | 12 ++++++++---- target/ppc/cpu_init.c | 12 ++++++++---- target/riscv/cpu.c | 12 ++++++++---- target/rx/cpu.c | 13 ++++++++----- target/sh4/cpu.c | 12 ++++++++---- target/sparc/cpu.c | 12 ++++++++---- target/tricore/cpu.c | 12 ++++++++---- target/xtensa/cpu.c | 12 ++++++++---- 37 files changed, 184 insertions(+), 110 deletions(-) Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson