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([2605:ef80:8015:12b0:403e:a15b:ff5e:d439]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b00561382a5a25sm1240357pfp.26.2022.10.04.07.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 07:10:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org Subject: [PATCH v7 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL Date: Tue, 4 Oct 2022 07:10:33 -0700 Message-Id: <20221004141051.110653-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Changes for v7: * Added stub for --disable-tcg (stsquad) * Re-worded the commit for patch 13 (stsquad) * Split out some more helpers around ifdefs in patch 18 (stsquad) Patches needing review: 13-accel-tcg-Do-not-align-tb-page_addr-0.patch 17-accel-tcg-Introduce-tb_pc-and-log_pc.patch 18-accel-tcg-Introduce-TARGET_TB_PCREL.patch r~ Alex Bennée (3): cpu: cache CPUClass in CPUState for hot code paths hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs cputlb: used cached CPUClass in our hot-paths Richard Henderson (15): accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull accel/tcg: Drop addr member from SavedIOTLB accel/tcg: Suppress auto-invalidate in probe_access_internal accel/tcg: Introduce probe_access_full accel/tcg: Introduce tlb_set_page_full include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA accel/tcg: Remove PageDesc code_bitmap accel/tcg: Use bool for page_find_alloc accel/tcg: Use DisasContextBase in plugin_gen_tb_start accel/tcg: Do not align tb->page_addr[0] accel/tcg: Inline tb_flush_jmp_cache include/hw/core: Create struct CPUJumpCache hw/core: Add CPUClass.get_pc accel/tcg: Introduce tb_pc and log_pc accel/tcg: Introduce TARGET_TB_PCREL accel/tcg/internal.h | 10 + accel/tcg/tb-hash.h | 1 + accel/tcg/tb-jmp-cache.h | 65 ++++++ include/exec/cpu-common.h | 1 + include/exec/cpu-defs.h | 48 ++++- include/exec/exec-all.h | 75 ++++++- include/exec/plugin-gen.h | 7 +- include/hw/core/cpu.h | 28 ++- include/qemu/typedefs.h | 2 + include/tcg/tcg.h | 2 +- accel/stubs/tcg-stub.c | 4 + accel/tcg/cpu-exec.c | 80 ++++---- accel/tcg/cputlb.c | 259 ++++++++++++++---------- accel/tcg/plugin-gen.c | 22 +- accel/tcg/translate-all.c | 214 +++++++++----------- accel/tcg/translator.c | 2 +- cpu.c | 9 +- hw/core/cpu-common.c | 3 +- hw/core/cpu-sysemu.c | 5 +- plugins/core.c | 2 +- target/alpha/cpu.c | 9 + target/arm/cpu.c | 17 +- target/arm/mte_helper.c | 14 +- target/arm/sve_helper.c | 4 +- target/arm/translate-a64.c | 2 +- target/avr/cpu.c | 10 +- target/cris/cpu.c | 8 + target/hexagon/cpu.c | 10 +- target/hppa/cpu.c | 12 +- target/i386/cpu.c | 9 + target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 11 +- target/m68k/cpu.c | 8 + target/microblaze/cpu.c | 10 +- target/mips/cpu.c | 8 + target/mips/tcg/exception.c | 2 +- target/mips/tcg/sysemu/special_helper.c | 2 +- target/nios2/cpu.c | 9 + target/openrisc/cpu.c | 10 +- target/ppc/cpu_init.c | 8 + target/riscv/cpu.c | 17 +- target/rx/cpu.c | 10 +- target/s390x/cpu.c | 8 + target/s390x/tcg/mem_helper.c | 4 - target/sh4/cpu.c | 12 +- target/sparc/cpu.c | 10 +- target/tricore/cpu.c | 11 +- target/xtensa/cpu.c | 8 + tcg/tcg.c | 8 +- trace/control-target.c | 2 +- 50 files changed, 739 insertions(+), 355 deletions(-) create mode 100644 accel/tcg/tb-jmp-cache.h