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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d62c2000000b0022afce9ea93sm9897856wrv.40.2022.10.03.09.23.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Oct 2022 09:23:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 0/3] target/arm: Enforce implemented granule size limits Date: Mon, 3 Oct 2022 17:23:12 +0100 Message-Id: <20221003162315.2833797-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Arm CPUs support some subset of the granule (page) sizes 4K, 16K and 64K. The guest selects the one it wants using bits in the TCR_ELx registers. If it tries to program these registers with a value that is either reserved or which requests a size that the CPU does not implement, the architecture requires that the CPU behaves as if the field was programmed to some size that has been implemented. Currently we don't implement this, and instead let the guest use any granule size, even if the CPU ID register fields say it isn't present. Patch 1 in this series makes us enforce this architectural requirement (the main effect will be that we stop incorrectly implementing 16K granules on most of the non-cpu-max CPUs). Patch 2 is new in v2, and extends the use of the new ARMGranuleSize enum to the ARMVAParameters struct. Patch 3 adds FEAT_GTG to the list of supported features, because all this feature really is is the definition of the separate fields for stage1 and stage2 granule support in ID_AA64MMFR0_EL1, and we already updated -cpu max to report its granule support that way when we were adding the LPA2 support. v1->v2 changes: * renamed the enum to ARMGranuleSize, moved it to internals.h * new patch 2 Patch 2 is the only unreviewed one. thanks -- PMM Peter Maydell (3): target/arm: Don't allow guest to use unimplemented granule sizes target/arm: Use ARMGranuleSize in ARMVAParameters docs/system/arm/emulation.rst: Report FEAT_GTG support docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 33 ++++++++ target/arm/internals.h | 32 +++++++- target/arm/helper.c | 137 +++++++++++++++++++++++++++++----- target/arm/ptw.c | 8 +- 5 files changed, 185 insertions(+), 26 deletions(-)