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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.23.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:23:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 00/42] target/arm: Implement FEAT_HAFDBS Date: Sat, 1 Oct 2022 09:22:36 -0700 Message-Id: <20221001162318.153420-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f29; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a major reorg to arm page table walking. While the result here is "merely" Hardware-assited Access Flag and Dirty Bit Setting (HAFDBS), the ultimate goal is the Realm Management Extension (RME). RME "recommends" that HAFDBS be implemented (I_CSLWZ). For HAFDBS, being able to find a host pointer for the ram that backs a given page table entry is required in order to perform the atomic update to that PTE. The easiest way to find a host pointer is to use the existing softtlb mechanism. Thus all of the page table walkers have been adjusted to take an mmu_idx that corresponds to the regime in which the page table is stored. In some cases, this is a new "physical" mmu_idx that has a permanent 1-1 mapping. For RME, "physical" addresses also have page permissions, coming from the Root realm Granule Protection Table, which can be thought of as a third stage page table lookup. So eventually the new Secure and Nonsecure physical mmu indexes will joined by Realm and Root physical mmu indexes, and all of them will take the new Granule Page Table into account. Previously, we had A-profile allocate separate mmu_idx for secure vs non-secure. I've done away with that. Now, I flush all mmu_idx when SCR_EL3.NS is changed. I did not see how we could reasonably add 8 more mmu_idx for Realm. Moreover, I had a look through ARM Trusted Firmware, at the code paths used to change between Secure and Nonsecure. We wind up flushing all of these mmu_idx anyway while swapping the EL1+EL2 cpregs, so there is no gain at all in attempting to keep them live at the same time within qemu. Changes for v3: * 20-odd patches upstreamed. * Changes to the base CPUTLBEntryFull patch set, propogated. * Queries via arm_cpu_get_phys_page_attrs_debug, i.e. gdbstub, do not use the softmmu tlb, and so do not modify cpu state. r~ Based-on: 20220930212622.108363-1-richard.henderson@linaro.org ("[PATCH v6 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL") Richard Henderson (42): target/arm: Split s2walk_secure from ipa_secure in get_phys_addr target/arm: Add is_secure parameter to get_phys_addr_lpae target/arm: Fix S2 disabled check in S1_ptw_translate target/arm: Add is_secure parameter to regime_translation_disabled target/arm: Split out get_phys_addr_with_secure target/arm: Add is_secure parameter to v7m_read_half_insn target/arm: Add TBFLAG_M32.SECURE target/arm: Merge regime_is_secure into get_phys_addr target/arm: Add is_secure parameter to do_ats_write target/arm: Fold secure and non-secure a-profile mmu indexes target/arm: Reorg regime_translation_disabled target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M target/arm: Introduce arm_hcr_el2_eff_secstate target/arm: Hoist read of *is_secure in S1_ptw_translate target/arm: Remove env argument from combined_attrs_fwb target/arm: Pass HCR to attribute subroutines. target/arm: Fix ATS12NSO* from S PL1 target/arm: Split out get_phys_addr_disabled target/arm: Fix cacheattr in get_phys_addr_disabled target/arm: Use tlb_set_page_full target/arm: Enable TARGET_PAGE_ENTRY_EXTRA target/arm: Use probe_access_full for MTE target/arm: Use probe_access_full for BTI target/arm: Add ARMMMUIdx_Phys_{S,NS} target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx target/arm: Plumb debug into S1_ptw_translate target/arm: Use softmmu tlbs for page table walking target/arm: Split out get_phys_addr_twostage target/arm: Use bool consistently for get_phys_addr subroutines target/arm: Add ptw_idx argument to S1_ptw_translate target/arm: Add isar predicates for FEAT_HAFDBS target/arm: Extract HA and HD in aa64_va_parameters target/arm: Split out S1TranslateResult type target/arm: Move be test for regime into S1TranslateResult target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw target/arm: Add ARMFault_UnsuppAtomicUpdate target/arm: Remove loop from get_phys_addr_lpae target/arm: Fix fault reporting in get_phys_addr_lpae target/arm: Don't shift attrs in get_phys_addr_lpae target/arm: Consider GP an attribute in get_phys_addr_lpae target/arm: Implement FEAT_HAFDBS target/arm: Use the max page size in a 2-stage ptw docs/system/arm/emulation.rst | 1 + target/arm/cpu-param.h | 10 +- target/arm/cpu.h | 143 ++-- target/arm/internals.h | 125 ++- target/arm/sve_ldst_internal.h | 1 + target/arm/cpu64.c | 1 + target/arm/helper.c | 200 +++-- target/arm/m_helper.c | 29 +- target/arm/mte_helper.c | 61 +- target/arm/ptw.c | 1315 ++++++++++++++++++++------------ target/arm/sve_helper.c | 54 +- target/arm/tlb_helper.c | 31 +- target/arm/translate-a64.c | 30 +- target/arm/translate.c | 9 +- 14 files changed, 1113 insertions(+), 897 deletions(-)