| Message ID | 20220822152741.1617527-1-richard.henderson@linaro.org |
|---|---|
| Headers | show |
| Series | target/arm: Implement FEAT_HAFDBS | expand |
On Mon, 22 Aug 2022 at 16:28, Richard Henderson <richard.henderson@linaro.org> wrote: > > This is a major reorg to arm page table walking. While the result > here is "merely" Hardware-assited Access Flag and Dirty Bit Setting > (HAFDBS), the ultimate goal is the Realm Management Extension (RME). > RME "recommends" that HAFDBS be implemented (I_CSLWZ). > > For HAFDBS, being able to find a host pointer for the ram that > backs a given page table entry is required in order to perform the > atomic update to that PTE. The easiest way to find a host pointer > is to use the existing softtlb mechanism. Thus all of the page > table walkers have been adjusted to take an mmu_idx that corresponds > to the regime in which the page table is stored. In some cases, > this is a new "physical" mmu_idx that has a permanent 1-1 mapping. > > For RME, "physical" addresses also have page permissions, coming > from the Root realm Granule Protection Table, which can be thought > of as a third stage page table lookup. So eventually the new > Secure and Nonsecure physical mmu indexes will joined by > Realm and Root physical mmu indexes, and all of them will take > the new Granule Page Table into account. > > Previously, we had A-profile allocate separate mmu_idx for secure > vs non-secure. I've done away with that. Now, I flush all mmu_idx > when SCR_EL3.NS is changed. I did not see how we could reasonably > add 8 more mmu_idx for Realm. Moreover, I had a look through ARM > Trusted Firmware, at the code paths used to change between Secure > and Nonsecure. We wind up flushing all of these mmu_idx anyway while > swapping the EL1+EL2 cpregs, so there is no gain at all in attempting > to keep them live at the same time within qemu. Hi; I'm going to take patches 1, 3-16, 18 and 20 into target-arm.next: > target/arm: Create GetPhysAddrResult > target/arm: Use GetPhysAddrResult in get_phys_addr_lpae > target/arm: Use GetPhysAddrResult in get_phys_addr_v6 > target/arm: Use GetPhysAddrResult in get_phys_addr_v5 > target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5 > target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7 > target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8 > target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup > target/arm: Remove is_subpage argument to pmsav8_mpu_lookup > target/arm: Add is_secure parameter to v8m_security_lookup > target/arm: Add secure parameter to pmsav8_mpu_lookup > target/arm: Add is_secure parameter to get_phys_addr_v5 > target/arm: Add is_secure parameter to get_phys_addr_v6 > target/arm: Add secure parameter to get_phys_addr_pmsav8 > target/arm: Add is_secure parameter to pmsav7_use_background_region > target/arm: Add secure parameter to get_phys_addr_pmsav7 > target/arm: Add is_secure parameter to get_phys_addr_pmsav5 I haven't looked at the second half of the patchset yet -- I'll come back to this after having worked through the rest of my to-review queue. thanks -- PMM
This is a major reorg to arm page table walking. While the result here is "merely" Hardware-assited Access Flag and Dirty Bit Setting (HAFDBS), the ultimate goal is the Realm Management Extension (RME). RME "recommends" that HAFDBS be implemented (I_CSLWZ). For HAFDBS, being able to find a host pointer for the ram that backs a given page table entry is required in order to perform the atomic update to that PTE. The easiest way to find a host pointer is to use the existing softtlb mechanism. Thus all of the page table walkers have been adjusted to take an mmu_idx that corresponds to the regime in which the page table is stored. In some cases, this is a new "physical" mmu_idx that has a permanent 1-1 mapping. For RME, "physical" addresses also have page permissions, coming from the Root realm Granule Protection Table, which can be thought of as a third stage page table lookup. So eventually the new Secure and Nonsecure physical mmu indexes will joined by Realm and Root physical mmu indexes, and all of them will take the new Granule Page Table into account. Previously, we had A-profile allocate separate mmu_idx for secure vs non-secure. I've done away with that. Now, I flush all mmu_idx when SCR_EL3.NS is changed. I did not see how we could reasonably add 8 more mmu_idx for Realm. Moreover, I had a look through ARM Trusted Firmware, at the code paths used to change between Secure and Nonsecure. We wind up flushing all of these mmu_idx anyway while swapping the EL1+EL2 cpregs, so there is no gain at all in attempting to keep them live at the same time within qemu. Major changes for v2: * Sort as much pure arm cleanup to the front. Most, but not all, of the first 20 have been reviewed. * The accel/tcg changes are completely different. I have renamed the IOTLB, because it's no longer IO specific. I've dropped the PageEntryExtra struct, and standardized on the renamed CPUTLBEntryFull struct, which now includes the phys_addr, page protection, and log2 page size; the target-specific fields are included via macro. The whole CPUTLBEntryFull struct is passed to the new tlb_set_page_full, simplifying usage; the struct is returned by the new probe_access_full. I've been working on an x86_64 conversion to CPUTLBEntryFull as well, both to figure out what another target needs, and to fix https://gitlab.com/qemu-project/qemu/-/issues/279 r~ Richard Henderson (66): target/arm: Create GetPhysAddrResult target/arm: Fix ipa_secure in get_phys_addr target/arm: Use GetPhysAddrResult in get_phys_addr_lpae target/arm: Use GetPhysAddrResult in get_phys_addr_v6 target/arm: Use GetPhysAddrResult in get_phys_addr_v5 target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5 target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7 target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8 target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup target/arm: Remove is_subpage argument to pmsav8_mpu_lookup target/arm: Add is_secure parameter to v8m_security_lookup target/arm: Add secure parameter to pmsav8_mpu_lookup target/arm: Add is_secure parameter to get_phys_addr_v5 target/arm: Add is_secure parameter to get_phys_addr_v6 target/arm: Add secure parameter to get_phys_addr_pmsav8 target/arm: Add is_secure parameter to pmsav7_use_background_region target/arm: Add is_secure parameter to get_phys_addr_lpae target/arm: Add secure parameter to get_phys_addr_pmsav7 target/arm: Add is_secure parameter to regime_translation_disabled target/arm: Add is_secure parameter to get_phys_addr_pmsav5 target/arm: Split out get_phys_addr_with_secure target/arm: Add is_secure parameter to v7m_read_half_insn target/arm: Add TBFLAG_M32.SECURE target/arm: Merge regime_is_secure into get_phys_addr target/arm: Add is_secure parameter to do_ats_write target/arm: Fold secure and non-secure a-profile mmu indexes target/arm: Reorg regime_translation_disabled target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M target/arm: Introduce arm_hcr_el2_eff_secstate target/arm: Hoist read of *is_secure in S1_ptw_translate target/arm: Fix S2 disabled check in S1_ptw_translate target/arm: Remove env argument from combined_attrs_fwb target/arm: Pass HCR to attribute subroutines. target/arm: Fix ATS12NSO* from S PL1 target/arm: Split out get_phys_addr_disabled target/arm: Reorg get_phys_addr_disabled accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull accel/tcg: Drop addr member from SavedIOTLB accel/tcg: Suppress auto-invalidate in probe_access_internal accel/tcg: Introduce probe_access_full accel/tcg: Introduce tlb_set_page_full target/arm: Use tlb_set_page_full include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA target/arm: Enable TARGET_PAGE_ENTRY_EXTRA target/arm: Use probe_access_full for MTE target/arm: Use probe_access_full for BTI include/exec: Remove target_tlb_bitN from MemTxAttrs target/arm: Add ARMMMUIdx_Phys_{S,NS} target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx target/arm: Use softmmu tlbs for page table walking target/arm: Hoist check for disabled stage2 translation. target/arm: Split out get_phys_addr_twostage target/arm: Use bool consistently for get_phys_addr subroutines target/arm: Only use ARMMMUIdx_Stage1* for two-stage translation target/arm: Add ptw_idx argument to S1_ptw_translate target/arm: Add isar predicates for FEAT_HAFDBS target/arm: Extract HA and HD in aa64_va_parameters target/arm: Split out S1TranslateResult type target/arm: Move be test for regime into S1TranslateResult target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw target/arm: Add ARMFault_UnsuppAtomicUpdate target/arm: Remove loop from get_phys_addr_lpae target/arm: Fix fault reporting in get_phys_addr_lpae target/arm: Don't shift attrs in get_phys_addr_lpae target/arm: Consider GP an attribute in get_phys_addr_lpae target/arm: Implement FEAT_HAFDBS docs/system/arm/emulation.rst | 1 + include/exec/cpu-defs.h | 45 +- include/exec/exec-all.h | 33 + include/exec/memattrs.h | 10 - include/hw/core/cpu.h | 1 - target/arm/cpu-param.h | 10 +- target/arm/cpu.h | 138 ++-- target/arm/internals.h | 109 +-- target/arm/sve_ldst_internal.h | 1 + accel/tcg/cputlb.c | 214 ++--- target/arm/cpu64.c | 1 + target/arm/helper.c | 213 +++-- target/arm/m_helper.c | 83 +- target/arm/mte_helper.c | 63 +- target/arm/ptw.c | 1343 +++++++++++++++++++------------- target/arm/sve_helper.c | 54 +- target/arm/tlb_helper.c | 39 +- target/arm/translate-a64.c | 30 +- target/arm/translate.c | 9 +- target/s390x/tcg/mem_helper.c | 4 - 20 files changed, 1287 insertions(+), 1114 deletions(-)