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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.23.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:23:59 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 00/10] target/arm: Implement FEAT_PMUv3p5 Date: Mon, 22 Aug 2022 14:23:48 +0100 Message-Id: <20220822132358.3524971-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This patchset implements the Armv8.5 feature FEAT_PMUv3p5, which is a set of minor enhancements to the PMU: * EL2 and EL3 can now prohibit the cycle counter from counting when in EL2 or when Secure, using new MDCR_EL2.HCCD and MDCR_EL3.SCCD bits * event counters are now 64 bits, with the overflow detection configurably at the 32 bit or 64 bit mark It also fixes a set of bugs in the existing PMU emulation which I discovered while trying to test my additions. This is of course all intended for 7.2. Changes v1->v2: * fixed indent error, comment typo * a non-change: opted not to use bitwise |= for bool * fixed patch 8 to implement MDCR_EL3.SCCD, not some weird mix of MCCD and SCCD * update emulation.rst to note feature is implemented Patch 8 is the only one that needs review. thanks -- PMM Peter Maydell (10): target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows target/arm: Correct value returned by pmu_counter_mask() target/arm: Don't mishandle count when enabling or disabling PMU counters target/arm: Ignore PMCR.D when PMCR.LC is set target/arm: Honour MDCR_EL2.HPMD in Secure EL2 target/arm: Detect overflow when calculating next PMU interrupt target/arm: Rename pmu_8_n feature test functions target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits target/arm: Support 64-bit event counters for FEAT_PMUv3p5 target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max' docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 37 +++++-- target/arm/internals.h | 5 +- target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 2 +- target/arm/helper.c | 198 +++++++++++++++++++++++++++------- 6 files changed, 192 insertions(+), 53 deletions(-)