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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p22-20020a7bcc96000000b003a52969e89csm8154985wma.4.2022.08.19.04.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Aug 2022 04:00:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/6] target/arm: Fix v8 AArch32 RAZ ID regs; implement FEAT_ETS Date: Fri, 19 Aug 2022 12:00:46 +0100 Message-Id: <20220819110052.2942289-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The main aim of this patchset is to implement FEAT_ETS. FEAT_ETS provides tighter guarantees on some memory orderings involving translation table walks that permit guest code to skip the context-synchronization event they would otherwise need to do after a TLB maintenance operation. QEMU already provides the tighter guarantees this feature requires, so all we need to do is advertise it in the ID registers... ...except that it turns out that for AArch32 this is done in ID_MMFR5, which is a new-in-v8.6 register that we don't implement yet. So we need to provide it. And while I was doing that I noticed that we accidentally forgot to implement a big chunk of the "reserved for future ID registers, must RAZ" cp15 space for v8 AArch32. So the big bit of the patchset is sorting that out :-) thanks -- PMM Peter Maydell (6): target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8 target/arm: Sort KVM reads of AArch32 ID registers into encoding order target/arm: Implement ID_MMFR5 target/arm: Implement ID_DFR1 target/arm: Advertise FEAT_ETS for '-cpu max' target/arm: Add missing space in comment docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 2 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 6 ++- target/arm/helper.c | 69 +++++++++++++++++++++++++++++++---- target/arm/kvm64.c | 8 +++- 6 files changed, 77 insertions(+), 10 deletions(-)