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[00/10] target/arm: Implement FEAT_PMUv3p5

Message ID 20220811171619.1154755-1-peter.maydell@linaro.org
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Series target/arm: Implement FEAT_PMUv3p5 | expand

Message

Peter Maydell Aug. 11, 2022, 5:16 p.m. UTC 
This patchset implements the Armv8.5 feature FEAT_PMUv3p5, which is
a set of minor enhancements to the PMU:
 * EL2 and EL3 can now prohibit the cycle counter from counting
   when in EL2 or when Secure, using new MDCR_EL2.HCCD and
   MDCR_EL3.SCCD bits
 * event counters are now 64 bits, with the overflow detection
   configurably at the 32 bit or 64 bit mark

It also fixes a set of bugs in the existing PMU emulation which I
discovered while trying to test my additions.

This is of course all intended for 7.2.

thanks
-- PMM

Peter Maydell (10):
  target/arm: Don't corrupt high half of PMOVSR when cycle counter
    overflows
  target/arm: Correct value returned by pmu_counter_mask()
  target/arm: Don't mishandle count when enabling or disabling PMU
    counters
  target/arm: Ignore PMCR.D when PMCR.LC is set
  target/arm: Honour MDCR_EL2.HPMD in Secure EL2
  target/arm: Detect overflow when calculating next PMU interrupt
  target/arm: Rename pmu_8_n feature test functions
  target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits
  target/arm: Support 64-bit event counters for FEAT_PMUv3p5
  target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'

 target/arm/cpu.h       |  37 ++++++--
 target/arm/internals.h |   5 +-
 target/arm/cpu64.c     |   2 +-
 target/arm/cpu_tcg.c   |   2 +-
 target/arm/helper.c    | 197 ++++++++++++++++++++++++++++++++---------
 5 files changed, 190 insertions(+), 53 deletions(-)